2007-10-28 23:42:18 +00:00
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/*
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* PowerMac NVRAM emulation
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*
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* Copyright (c) 2005-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2007-11-17 17:14:51 +00:00
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#include "hw.h"
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2008-12-24 20:26:14 +00:00
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#include "firmware_abi.h"
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#include "sysemu.h"
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2007-10-28 23:42:18 +00:00
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#include "ppc_mac.h"
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2008-12-24 09:38:16 +00:00
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/* debug NVR */
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//#define DEBUG_NVR
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#ifdef DEBUG_NVR
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#define NVR_DPRINTF(fmt, args...) \
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do { printf("NVR: " fmt , ##args); } while (0)
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#else
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#define NVR_DPRINTF(fmt, args...)
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#endif
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2007-10-28 23:42:18 +00:00
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struct MacIONVRAMState {
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2007-11-04 01:16:04 +00:00
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target_phys_addr_t size;
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int mem_index;
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2008-12-26 23:05:15 +00:00
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uint8_t *data;
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2007-10-28 23:42:18 +00:00
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};
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2008-12-26 23:05:23 +00:00
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#define DEF_SYSTEM_SIZE 0xc10
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2007-10-28 23:42:18 +00:00
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/* Direct access to NVRAM */
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uint32_t macio_nvram_read (void *opaque, uint32_t addr)
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{
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MacIONVRAMState *s = opaque;
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uint32_t ret;
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2008-12-26 23:05:15 +00:00
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if (addr < s->size)
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2007-10-28 23:42:18 +00:00
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ret = s->data[addr];
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else
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ret = -1;
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2008-12-24 09:38:16 +00:00
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NVR_DPRINTF("read addr %04x val %x\n", addr, ret);
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2007-10-28 23:42:18 +00:00
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return ret;
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}
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void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val)
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{
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MacIONVRAMState *s = opaque;
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2008-12-24 09:38:16 +00:00
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NVR_DPRINTF("write addr %04x val %x\n", addr, val);
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2008-12-26 23:05:15 +00:00
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if (addr < s->size)
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2007-10-28 23:42:18 +00:00
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s->data[addr] = val;
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}
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/* macio style NVRAM device */
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static void macio_nvram_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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MacIONVRAMState *s = opaque;
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2007-11-04 01:16:04 +00:00
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2008-12-26 23:05:15 +00:00
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addr = (addr >> 4) & (s->size - 1);
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2007-10-28 23:42:18 +00:00
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s->data[addr] = value;
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2008-12-24 09:38:16 +00:00
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NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
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2007-10-28 23:42:18 +00:00
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}
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static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
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{
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MacIONVRAMState *s = opaque;
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uint32_t value;
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2008-12-26 23:05:15 +00:00
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addr = (addr >> 4) & (s->size - 1);
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2007-10-28 23:42:18 +00:00
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value = s->data[addr];
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2008-12-24 09:38:16 +00:00
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NVR_DPRINTF("readb addr %04x val %x\n", (int)addr, value);
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2007-10-28 23:42:18 +00:00
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return value;
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}
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static CPUWriteMemoryFunc *nvram_write[] = {
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&macio_nvram_writeb,
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&macio_nvram_writeb,
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&macio_nvram_writeb,
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};
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static CPUReadMemoryFunc *nvram_read[] = {
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&macio_nvram_readb,
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&macio_nvram_readb,
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&macio_nvram_readb,
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};
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2008-12-30 19:01:19 +00:00
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static void macio_nvram_save(QEMUFile *f, void *opaque)
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{
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MacIONVRAMState *s = (MacIONVRAMState *)opaque;
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qemu_put_buffer(f, s->data, s->size);
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}
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static int macio_nvram_load(QEMUFile *f, void *opaque, int version_id)
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{
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MacIONVRAMState *s = (MacIONVRAMState *)opaque;
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if (version_id != 1)
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return -EINVAL;
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qemu_get_buffer(f, s->data, s->size);
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return 0;
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}
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2008-12-28 18:27:10 +00:00
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static void macio_nvram_reset(void *opaque)
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{
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}
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2007-11-04 01:16:04 +00:00
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MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size)
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2007-10-28 23:42:18 +00:00
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{
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MacIONVRAMState *s;
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2007-11-04 01:16:04 +00:00
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2007-10-28 23:42:18 +00:00
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s = qemu_mallocz(sizeof(MacIONVRAMState));
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2008-12-26 23:05:15 +00:00
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s->data = qemu_mallocz(size);
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2007-11-04 01:16:04 +00:00
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s->size = size;
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2008-12-26 23:05:15 +00:00
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2007-11-04 01:16:04 +00:00
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s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
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*mem_index = s->mem_index;
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2008-12-30 19:01:19 +00:00
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register_savevm("macio_nvram", -1, 1, macio_nvram_save, macio_nvram_load,
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s);
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2008-12-28 18:27:10 +00:00
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qemu_register_reset(macio_nvram_reset, s);
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macio_nvram_reset(s);
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2007-10-28 23:42:18 +00:00
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return s;
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}
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2007-11-04 01:16:04 +00:00
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void macio_nvram_map (void *opaque, target_phys_addr_t mem_base)
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{
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MacIONVRAMState *s;
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s = opaque;
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2008-12-26 23:05:15 +00:00
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cpu_register_physical_memory(mem_base, s->size << 4, s->mem_index);
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2007-11-04 01:16:04 +00:00
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}
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2008-12-24 20:26:14 +00:00
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/* Set up a system OpenBIOS NVRAM partition */
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2007-10-28 23:42:18 +00:00
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void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len)
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{
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2008-12-24 20:26:14 +00:00
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unsigned int i;
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uint32_t start = 0, end;
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struct OpenBIOS_nvpart_v1 *part_header;
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// OpenBIOS nvram variables
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// Variable partition
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part_header = (struct OpenBIOS_nvpart_v1 *)nvr->data;
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part_header->signature = OPENBIOS_PART_SYSTEM;
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pstrcpy(part_header->name, sizeof(part_header->name), "system");
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end = start + sizeof(struct OpenBIOS_nvpart_v1);
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for (i = 0; i < nb_prom_envs; i++)
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end = OpenBIOS_set_var(nvr->data, end, prom_envs[i]);
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// End marker
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nvr->data[end++] = '\0';
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end = start + ((end - start + 15) & ~15);
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2008-12-26 23:05:23 +00:00
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/* XXX: OpenBIOS is not able to grow up a partition. Leave some space for
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new variables. */
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if (end < DEF_SYSTEM_SIZE)
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end = DEF_SYSTEM_SIZE;
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2008-12-24 20:26:14 +00:00
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OpenBIOS_finish_partition(part_header, end - start);
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// free partition
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start = end;
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part_header = (struct OpenBIOS_nvpart_v1 *)&nvr->data[start];
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part_header->signature = OPENBIOS_PART_FREE;
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pstrcpy(part_header->name, sizeof(part_header->name), "free");
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end = len;
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OpenBIOS_finish_partition(part_header, end - start);
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2007-10-28 23:42:18 +00:00
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}
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