2015-03-11 13:21:06 +00:00
|
|
|
/*
|
|
|
|
* STM32F205 SoC
|
|
|
|
*
|
|
|
|
* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
|
|
|
|
*
|
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
|
|
* in the Software without restriction, including without limitation the rights
|
|
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
|
|
* furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice shall be included in
|
|
|
|
* all copies or substantial portions of the Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
|
|
* THE SOFTWARE.
|
|
|
|
*/
|
|
|
|
|
2015-12-07 16:23:45 +00:00
|
|
|
#include "qemu/osdep.h"
|
include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 08:01:28 +00:00
|
|
|
#include "qapi/error.h"
|
2019-05-23 14:35:07 +00:00
|
|
|
#include "qemu/module.h"
|
2019-05-23 13:47:43 +00:00
|
|
|
#include "hw/arm/boot.h"
|
2015-03-11 13:21:06 +00:00
|
|
|
#include "exec/address-spaces.h"
|
|
|
|
#include "hw/arm/stm32f205_soc.h"
|
2019-08-12 05:23:51 +00:00
|
|
|
#include "hw/qdev-properties.h"
|
2019-08-12 05:23:57 +00:00
|
|
|
#include "sysemu/sysemu.h"
|
2015-03-11 13:21:06 +00:00
|
|
|
|
|
|
|
/* At the moment only Timer 2 to 5 are modelled */
|
|
|
|
static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
|
|
|
|
0x40000800, 0x40000C00 };
|
|
|
|
static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
|
|
|
|
0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
|
2016-10-04 12:28:07 +00:00
|
|
|
static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
|
|
|
|
0x40012200 };
|
2016-10-04 12:28:07 +00:00
|
|
|
static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
|
|
|
|
0x40003C00 };
|
2015-03-11 13:21:06 +00:00
|
|
|
|
|
|
|
static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
|
|
|
|
static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
|
2016-10-04 12:28:07 +00:00
|
|
|
#define ADC_IRQ 18
|
2016-10-04 12:28:07 +00:00
|
|
|
static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
|
2015-03-11 13:21:06 +00:00
|
|
|
|
|
|
|
static void stm32f205_soc_initfn(Object *obj)
|
|
|
|
{
|
|
|
|
STM32F205State *s = STM32F205_SOC(obj);
|
|
|
|
int i;
|
|
|
|
|
2018-07-16 12:59:32 +00:00
|
|
|
sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
|
|
|
|
TYPE_ARMV7M);
|
2017-02-20 15:36:04 +00:00
|
|
|
|
2018-07-16 12:59:32 +00:00
|
|
|
sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
|
|
|
|
TYPE_STM32F2XX_SYSCFG);
|
2015-03-11 13:21:06 +00:00
|
|
|
|
|
|
|
for (i = 0; i < STM_NUM_USARTS; i++) {
|
2018-07-16 12:59:32 +00:00
|
|
|
sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
|
|
|
|
sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
|
2015-03-11 13:21:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < STM_NUM_TIMERS; i++) {
|
2018-07-16 12:59:32 +00:00
|
|
|
sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
|
|
|
|
sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
|
2015-03-11 13:21:06 +00:00
|
|
|
}
|
2016-10-04 12:28:07 +00:00
|
|
|
|
|
|
|
s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
|
|
|
|
|
|
|
|
for (i = 0; i < STM_NUM_ADCS; i++) {
|
2018-07-16 12:59:32 +00:00
|
|
|
sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
|
|
|
|
TYPE_STM32F2XX_ADC);
|
2016-10-04 12:28:07 +00:00
|
|
|
}
|
2016-10-04 12:28:07 +00:00
|
|
|
|
|
|
|
for (i = 0; i < STM_NUM_SPIS; i++) {
|
2018-07-16 12:59:32 +00:00
|
|
|
sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
|
|
|
|
TYPE_STM32F2XX_SPI);
|
2016-10-04 12:28:07 +00:00
|
|
|
}
|
2015-03-11 13:21:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
|
|
|
|
{
|
|
|
|
STM32F205State *s = STM32F205_SOC(dev_soc);
|
2017-02-20 15:36:05 +00:00
|
|
|
DeviceState *dev, *armv7m;
|
2016-10-04 12:28:06 +00:00
|
|
|
SysBusDevice *busdev;
|
2015-03-11 13:21:06 +00:00
|
|
|
Error *err = NULL;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
MemoryRegion *system_memory = get_system_memory();
|
|
|
|
MemoryRegion *sram = g_new(MemoryRegion, 1);
|
|
|
|
MemoryRegion *flash = g_new(MemoryRegion, 1);
|
|
|
|
MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
|
|
|
|
|
2017-07-07 14:42:53 +00:00
|
|
|
memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 14:51:43 +00:00
|
|
|
&error_fatal);
|
2015-03-11 13:21:06 +00:00
|
|
|
memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
|
|
|
|
flash, 0, FLASH_SIZE);
|
|
|
|
|
|
|
|
memory_region_set_readonly(flash, true);
|
|
|
|
memory_region_set_readonly(flash_alias, true);
|
|
|
|
|
|
|
|
memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
|
|
|
|
memory_region_add_subregion(system_memory, 0, flash_alias);
|
|
|
|
|
2017-07-07 14:42:53 +00:00
|
|
|
memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 14:51:43 +00:00
|
|
|
&error_fatal);
|
2015-03-11 13:21:06 +00:00
|
|
|
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
|
|
|
|
|
2017-02-20 15:36:05 +00:00
|
|
|
armv7m = DEVICE(&s->armv7m);
|
|
|
|
qdev_prop_set_uint32(armv7m, "num-irq", 96);
|
2017-09-13 16:04:57 +00:00
|
|
|
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
|
2018-08-16 13:05:28 +00:00
|
|
|
qdev_prop_set_bit(armv7m, "enable-bitband", true);
|
2017-02-20 15:36:04 +00:00
|
|
|
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
|
|
|
|
"memory", &error_abort);
|
|
|
|
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
|
|
|
|
if (err != NULL) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
2015-03-11 13:21:06 +00:00
|
|
|
|
|
|
|
/* System configuration controller */
|
2016-10-04 12:28:06 +00:00
|
|
|
dev = DEVICE(&s->syscfg);
|
2015-03-11 13:21:06 +00:00
|
|
|
object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
|
|
|
|
if (err != NULL) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
2016-10-04 12:28:06 +00:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_mmio_map(busdev, 0, 0x40013800);
|
2017-02-20 15:36:05 +00:00
|
|
|
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
|
2015-03-11 13:21:06 +00:00
|
|
|
|
|
|
|
/* Attach UART (uses USART registers) and USART controllers */
|
|
|
|
for (i = 0; i < STM_NUM_USARTS; i++) {
|
2016-10-04 12:28:06 +00:00
|
|
|
dev = DEVICE(&(s->usart[i]));
|
2018-04-20 14:52:44 +00:00
|
|
|
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
|
2015-03-11 13:21:06 +00:00
|
|
|
object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
|
|
|
|
if (err != NULL) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
2016-10-04 12:28:06 +00:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_mmio_map(busdev, 0, usart_addr[i]);
|
2017-02-20 15:36:05 +00:00
|
|
|
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
|
2015-03-11 13:21:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Timer 2 to 5 */
|
|
|
|
for (i = 0; i < STM_NUM_TIMERS; i++) {
|
2016-10-04 12:28:06 +00:00
|
|
|
dev = DEVICE(&(s->timer[i]));
|
|
|
|
qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
|
2015-03-11 13:21:06 +00:00
|
|
|
object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
|
|
|
|
if (err != NULL) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
2016-10-04 12:28:06 +00:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_mmio_map(busdev, 0, timer_addr[i]);
|
2017-02-20 15:36:05 +00:00
|
|
|
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
|
2015-03-11 13:21:06 +00:00
|
|
|
}
|
2016-10-04 12:28:07 +00:00
|
|
|
|
|
|
|
/* ADC 1 to 3 */
|
|
|
|
object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS,
|
|
|
|
"num-lines", &err);
|
|
|
|
object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
|
|
|
|
if (err != NULL) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
|
2017-02-20 15:36:05 +00:00
|
|
|
qdev_get_gpio_in(armv7m, ADC_IRQ));
|
2016-10-04 12:28:07 +00:00
|
|
|
|
|
|
|
for (i = 0; i < STM_NUM_ADCS; i++) {
|
|
|
|
dev = DEVICE(&(s->adc[i]));
|
|
|
|
object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
|
|
|
|
if (err != NULL) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_mmio_map(busdev, 0, adc_addr[i]);
|
|
|
|
sysbus_connect_irq(busdev, 0,
|
|
|
|
qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
|
|
|
|
}
|
2016-10-04 12:28:07 +00:00
|
|
|
|
|
|
|
/* SPI 1 and 2 */
|
|
|
|
for (i = 0; i < STM_NUM_SPIS; i++) {
|
|
|
|
dev = DEVICE(&(s->spi[i]));
|
|
|
|
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
|
|
|
|
if (err != NULL) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_mmio_map(busdev, 0, spi_addr[i]);
|
2017-02-20 15:36:05 +00:00
|
|
|
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
|
2016-10-04 12:28:07 +00:00
|
|
|
}
|
2015-03-11 13:21:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static Property stm32f205_soc_properties[] = {
|
2017-09-13 16:04:57 +00:00
|
|
|
DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
|
2015-03-11 13:21:06 +00:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
dc->realize = stm32f205_soc_realize;
|
|
|
|
dc->props = stm32f205_soc_properties;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo stm32f205_soc_info = {
|
|
|
|
.name = TYPE_STM32F205_SOC,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(STM32F205State),
|
|
|
|
.instance_init = stm32f205_soc_initfn,
|
|
|
|
.class_init = stm32f205_soc_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void stm32f205_soc_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&stm32f205_soc_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(stm32f205_soc_types)
|