xemu/hw/riscv/Makefile.objs

obj-y += riscv_htif.o
obj-y += riscv_hart.o
obj-y += sifive_e.o
obj-y += sifive_clint.o
obj-y += sifive_prci.o
obj-y += sifive_plic.o
obj-y += sifive_test.o
obj-y += sifive_u.o
obj-y += sifive_uart.o
obj-y += spike.o
obj-y += virt.o
RISC-V Build Infrastructure This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com> 2018-03-02 12:32:59 +00:00			`obj-y += riscv_htif.o`
			`obj-y += riscv_hart.o`
			`obj-y += sifive_e.o`
			`obj-y += sifive_clint.o`
			`obj-y += sifive_prci.o`
			`obj-y += sifive_plic.o`
			`obj-y += sifive_test.o`
			`obj-y += sifive_u.o`
			`obj-y += sifive_uart.o`
			`obj-y += spike.o`
			`obj-y += virt.o`