2008-02-03 02:20:18 +00:00
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/*******************************************************************************
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Intel PRO/1000 Linux driver
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Copyright(c) 1999 - 2006 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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2009-07-16 20:47:01 +00:00
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this program; if not, see <http://www.gnu.org/licenses/>.
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2008-02-03 02:20:18 +00:00
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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/* e1000_hw.h
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* Structures, enums, and macros for the MAC
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*/
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#ifndef _E1000_HW_H_
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#define _E1000_HW_H_
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/* PCI Device IDs */
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#define E1000_DEV_ID_82542 0x1000
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#define E1000_DEV_ID_82543GC_FIBER 0x1001
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#define E1000_DEV_ID_82543GC_COPPER 0x1004
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#define E1000_DEV_ID_82544EI_COPPER 0x1008
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#define E1000_DEV_ID_82544EI_FIBER 0x1009
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#define E1000_DEV_ID_82544GC_COPPER 0x100C
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#define E1000_DEV_ID_82544GC_LOM 0x100D
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#define E1000_DEV_ID_82540EM 0x100E
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#define E1000_DEV_ID_82540EM_LOM 0x1015
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#define E1000_DEV_ID_82540EP_LOM 0x1016
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#define E1000_DEV_ID_82540EP 0x1017
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#define E1000_DEV_ID_82540EP_LP 0x101E
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#define E1000_DEV_ID_82545EM_COPPER 0x100F
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#define E1000_DEV_ID_82545EM_FIBER 0x1011
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#define E1000_DEV_ID_82545GM_COPPER 0x1026
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#define E1000_DEV_ID_82545GM_FIBER 0x1027
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#define E1000_DEV_ID_82545GM_SERDES 0x1028
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#define E1000_DEV_ID_82546EB_COPPER 0x1010
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#define E1000_DEV_ID_82546EB_FIBER 0x1012
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#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
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#define E1000_DEV_ID_82541EI 0x1013
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#define E1000_DEV_ID_82541EI_MOBILE 0x1018
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#define E1000_DEV_ID_82541ER_LOM 0x1014
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#define E1000_DEV_ID_82541ER 0x1078
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#define E1000_DEV_ID_82547GI 0x1075
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#define E1000_DEV_ID_82541GI 0x1076
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#define E1000_DEV_ID_82541GI_MOBILE 0x1077
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#define E1000_DEV_ID_82541GI_LF 0x107C
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#define E1000_DEV_ID_82546GB_COPPER 0x1079
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#define E1000_DEV_ID_82546GB_FIBER 0x107A
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#define E1000_DEV_ID_82546GB_SERDES 0x107B
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#define E1000_DEV_ID_82546GB_PCIE 0x108A
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#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
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#define E1000_DEV_ID_82547EI 0x1019
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#define E1000_DEV_ID_82547EI_MOBILE 0x101A
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#define E1000_DEV_ID_82571EB_COPPER 0x105E
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#define E1000_DEV_ID_82571EB_FIBER 0x105F
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#define E1000_DEV_ID_82571EB_SERDES 0x1060
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#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
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#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
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#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
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#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
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#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
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#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
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#define E1000_DEV_ID_82572EI_COPPER 0x107D
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#define E1000_DEV_ID_82572EI_FIBER 0x107E
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#define E1000_DEV_ID_82572EI_SERDES 0x107F
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#define E1000_DEV_ID_82572EI 0x10B9
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#define E1000_DEV_ID_82573E 0x108B
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#define E1000_DEV_ID_82573E_IAMT 0x108C
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#define E1000_DEV_ID_82573L 0x109A
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#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
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#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
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#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
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#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
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#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
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#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
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#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
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#define E1000_DEV_ID_ICH8_IGP_C 0x104B
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#define E1000_DEV_ID_ICH8_IFE 0x104C
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#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
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#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
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#define E1000_DEV_ID_ICH8_IGP_M 0x104D
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/* Register Set. (82543, 82544)
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*
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* Registers are defined to be 32 bits and should be accessed as 32 bit values.
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* These registers are physically located on the NIC, but are mapped into the
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* host memory address space.
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*
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* RW - register is both readable and writable
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* RO - register is read only
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* WO - register is write only
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* R/clr - register is read only and is cleared when read
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* A - register array
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*/
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#define E1000_CTRL 0x00000 /* Device Control - RW */
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#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
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#define E1000_STATUS 0x00008 /* Device Status - RO */
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#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
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#define E1000_EERD 0x00014 /* EEPROM Read - RW */
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#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
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#define E1000_FLA 0x0001C /* Flash Access - RW */
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#define E1000_MDIC 0x00020 /* MDI Control - RW */
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#define E1000_SCTL 0x00024 /* SerDes Control - RW */
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#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */
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#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
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#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
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#define E1000_FCT 0x00030 /* Flow Control Type - RW */
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#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
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#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
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#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
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#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
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#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
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#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
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#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
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#define E1000_RCTL 0x00100 /* RX Control - RW */
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#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
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#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
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#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
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#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
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#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
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#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
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#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
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#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
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#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
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#define E1000_TCTL 0x00400 /* TX Control - RW */
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#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
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#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
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#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
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#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
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#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
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#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
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#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
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#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
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#define FEXTNVM_SW_CONFIG 0x0001
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#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
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#define E1000_PBS 0x01008 /* Packet Buffer Size */
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#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
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#define E1000_FLASH_UPDATES 1000
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#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
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#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
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#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
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#define E1000_FLSWCTL 0x01030 /* FLASH control register */
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#define E1000_FLSWDATA 0x01034 /* FLASH data register */
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#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
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#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
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#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
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#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
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#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
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#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
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#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
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#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
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#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
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#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
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#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
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#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
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#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
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#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
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#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
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#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
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#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
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#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
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#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
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#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
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#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
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#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
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#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
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#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
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#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
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#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
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#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
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#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
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#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
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#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
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#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
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#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
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#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
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#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
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#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
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#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
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#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
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#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
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#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
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#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
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#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
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#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
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#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
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#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
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#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
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#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
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#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
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#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
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#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
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#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
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#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
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#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
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#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
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#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
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#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
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#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
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#define E1000_COLC 0x04028 /* Collision Count - R/clr */
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#define E1000_DC 0x04030 /* Defer Count - R/clr */
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#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
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#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
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#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
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#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
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#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
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#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
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#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
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#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
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#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
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#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
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#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
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#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
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#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
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#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
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#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
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#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
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#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
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#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
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#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
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#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
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#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
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#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
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#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
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#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
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#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
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#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
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#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
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#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
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#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
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#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
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#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
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#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
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#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
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#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
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#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
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#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
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#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
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#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
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#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
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#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
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#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
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#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
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#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
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#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
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#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
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#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
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#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
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#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
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#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
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#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
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#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
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#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
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#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
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#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
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#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
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#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
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#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
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#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
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#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
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#define E1000_RA 0x05400 /* Receive Address - RW Array */
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#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
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#define E1000_WUC 0x05800 /* Wakeup Control - RW */
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#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
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#define E1000_WUS 0x05810 /* Wakeup Status - RO */
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#define E1000_MANC 0x05820 /* Management Control - RW */
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#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
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#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
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#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
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#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
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#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
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#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
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#define E1000_HOST_IF 0x08800 /* Host Interface */
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#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
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#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
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#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
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#define E1000_MDPHYA 0x0003C /* PHY address - RW */
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2011-11-29 08:52:39 +00:00
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#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
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2008-02-03 02:20:18 +00:00
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#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
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#define E1000_GCR 0x05B00 /* PCI-Ex Control */
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#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
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#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
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#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
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#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
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#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
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#define E1000_SWSM 0x05B50 /* SW Semaphore */
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#define E1000_FWSM 0x05B54 /* FW Semaphore */
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#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
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#define E1000_HICR 0x08F00 /* Host Inteface Control */
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/* RSS registers */
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#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
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#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
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#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
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#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
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#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
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#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
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/* PHY 1000 MII Register/Bit Definitions */
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/* PHY Registers defined by IEEE */
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#define PHY_CTRL 0x00 /* Control Register */
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#define PHY_STATUS 0x01 /* Status Regiser */
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#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
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#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
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#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
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#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
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#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
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#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
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#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
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#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
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#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
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#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
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#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
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#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
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/* M88E1000 Specific Registers */
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#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
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#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
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#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
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#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
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#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
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#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
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#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
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#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
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#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
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#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
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#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
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|
|
2012-03-22 10:01:42 +00:00
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/* PHY Control Register */
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#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
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#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
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#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
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#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
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#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
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#define MII_CR_POWER_DOWN 0x0800 /* Power down */
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#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
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#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
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#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
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#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
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|
|
|
2011-08-17 09:03:14 +00:00
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/* PHY Status Register */
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#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
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#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
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#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
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#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
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#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
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#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
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#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
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#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
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#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
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#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
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#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
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#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
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#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
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#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
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#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
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|
|
2008-02-03 02:20:18 +00:00
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/* Interrupt Cause Read */
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|
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#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
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#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
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#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
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#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
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#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
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#define E1000_ICR_RXO 0x00000040 /* rx overrun */
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#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
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#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
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#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
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#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
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#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
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#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
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#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
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#define E1000_ICR_TXD_LOW 0x00008000
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#define E1000_ICR_SRPD 0x00010000
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#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
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#define E1000_ICR_MNG 0x00040000 /* Manageability event */
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#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
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#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
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#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
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#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
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#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */
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#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
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#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
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#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
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#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
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#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
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#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
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#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */
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/* Interrupt Cause Set */
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#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
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#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
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#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
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#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
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#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
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#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
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#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
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#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
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#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
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#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
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#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
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#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
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#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
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#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
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#define E1000_ICS_SRPD E1000_ICR_SRPD
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#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
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#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
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#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
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#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
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#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
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#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
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#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
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#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
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#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
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#define E1000_ICS_DSW E1000_ICR_DSW
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#define E1000_ICS_PHYINT E1000_ICR_PHYINT
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#define E1000_ICS_EPRST E1000_ICR_EPRST
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/* Interrupt Mask Set */
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#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
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#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
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#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
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#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
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#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
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#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
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#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
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#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
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#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
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#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
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#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
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#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
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#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
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#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
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#define E1000_IMS_SRPD E1000_ICR_SRPD
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#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
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#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
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#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
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#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
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#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
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#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
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#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
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#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
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#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
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#define E1000_IMS_DSW E1000_ICR_DSW
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#define E1000_IMS_PHYINT E1000_ICR_PHYINT
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#define E1000_IMS_EPRST E1000_ICR_EPRST
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/* Interrupt Mask Clear */
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#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
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#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
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#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
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#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
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#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
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#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
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#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
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#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
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#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
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#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
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#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
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#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
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#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
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#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
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#define E1000_IMC_SRPD E1000_ICR_SRPD
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#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
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#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
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#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
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#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
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#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
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#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
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#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
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#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
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#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
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#define E1000_IMC_DSW E1000_ICR_DSW
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#define E1000_IMC_PHYINT E1000_ICR_PHYINT
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#define E1000_IMC_EPRST E1000_ICR_EPRST
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/* Receive Control */
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#define E1000_RCTL_RST 0x00000001 /* Software reset */
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#define E1000_RCTL_EN 0x00000002 /* enable */
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#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
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#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
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#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
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#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
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#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
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#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
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#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
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#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
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#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
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#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
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#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
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#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
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#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
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#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
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#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
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#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
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#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
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#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
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#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
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#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
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/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
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#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
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#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
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#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
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#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
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/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
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#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
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#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
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#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
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#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
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#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
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#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
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#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
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#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
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#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
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#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
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#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
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#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
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#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
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#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
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#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
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2008-03-28 22:31:06 +00:00
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#define E1000_EEPROM_RW_REG_DONE 0x10 /* Offset to READ/WRITE done bit */
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2008-02-03 02:20:18 +00:00
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#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
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2008-03-28 22:31:06 +00:00
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#define E1000_EEPROM_RW_ADDR_SHIFT 8 /* Shift to the address bits */
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2008-02-03 02:20:18 +00:00
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#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
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#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
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/* Register Bit Masks */
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/* Device Control */
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#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
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#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
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#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
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#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
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#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
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#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
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#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
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#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
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#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
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#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
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#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
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#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
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#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
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#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
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#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
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#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
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#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
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#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
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#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
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#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
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#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
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#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
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#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
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#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
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#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
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#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
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#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
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#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
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#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
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#define E1000_CTRL_RST 0x04000000 /* Global reset */
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#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
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#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
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#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
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#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
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#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
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#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
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/* Device Status */
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#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
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#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
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#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
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#define E1000_STATUS_FUNC_SHIFT 2
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#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
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#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
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#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
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#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
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#define E1000_STATUS_SPEED_MASK 0x000000C0
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#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
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#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
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#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
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#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
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by EEPROM/Flash */
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#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
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#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
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#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
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#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
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#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
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#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
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#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
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#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
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#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
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#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
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#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
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#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
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#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */
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#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
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#define E1000_STATUS_FUSE_8 0x04000000
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#define E1000_STATUS_FUSE_9 0x08000000
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#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
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#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
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/* EEPROM/Flash Control */
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#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
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#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
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#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
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#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
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#define E1000_EECD_FWE_MASK 0x00000030
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#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
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#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
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#define E1000_EECD_FWE_SHIFT 4
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#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
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#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
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#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
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#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
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#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
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* (0-small, 1-large) */
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#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
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#ifndef E1000_EEPROM_GRANT_ATTEMPTS
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#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
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#endif
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#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
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#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
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#define E1000_EECD_SIZE_EX_SHIFT 11
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#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
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#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
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#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
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#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
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#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
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#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
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#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
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#define E1000_EECD_SECVAL_SHIFT 22
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#define E1000_STM_OPCODE 0xDB00
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#define E1000_HICR_FW_RESET 0xC0
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#define E1000_SHADOW_RAM_WORDS 2048
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#define E1000_ICH_NVM_SIG_WORD 0x13
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#define E1000_ICH_NVM_SIG_MASK 0xC0
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/* MDI Control */
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#define E1000_MDIC_DATA_MASK 0x0000FFFF
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#define E1000_MDIC_REG_MASK 0x001F0000
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#define E1000_MDIC_REG_SHIFT 16
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#define E1000_MDIC_PHY_MASK 0x03E00000
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#define E1000_MDIC_PHY_SHIFT 21
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#define E1000_MDIC_OP_WRITE 0x04000000
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#define E1000_MDIC_OP_READ 0x08000000
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#define E1000_MDIC_READY 0x10000000
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#define E1000_MDIC_INT_EN 0x20000000
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#define E1000_MDIC_ERROR 0x40000000
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/* EEPROM Commands - Microwire */
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#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
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#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
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#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
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#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
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#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
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/* EEPROM Word Offsets */
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#define EEPROM_COMPAT 0x0003
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#define EEPROM_ID_LED_SETTINGS 0x0004
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#define EEPROM_VERSION 0x0005
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#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
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#define EEPROM_PHY_CLASS_WORD 0x0007
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#define EEPROM_INIT_CONTROL1_REG 0x000A
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#define EEPROM_INIT_CONTROL2_REG 0x000F
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#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
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#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
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#define EEPROM_INIT_3GIO_3 0x001A
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#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
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#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
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#define EEPROM_CFG 0x0012
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#define EEPROM_FLASH_VERSION 0x0032
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#define EEPROM_CHECKSUM_REG 0x003F
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#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
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#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
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/* Transmit Descriptor */
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struct e1000_tx_desc {
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uint64_t buffer_addr; /* Address of the descriptor's data buffer */
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union {
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uint32_t data;
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struct {
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uint16_t length; /* Data buffer length */
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uint8_t cso; /* Checksum offset */
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uint8_t cmd; /* Descriptor control */
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} flags;
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} lower;
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union {
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uint32_t data;
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struct {
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uint8_t status; /* Descriptor status */
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uint8_t css; /* Checksum start */
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uint16_t special;
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} fields;
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} upper;
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};
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/* Transmit Descriptor bit definitions */
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#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
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#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
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#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
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#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
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#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
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#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
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#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
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#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
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#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
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#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
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#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
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#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
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#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
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#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
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#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
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#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
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#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
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#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
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#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
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#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
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/* Transmit Control */
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#define E1000_TCTL_RST 0x00000001 /* software reset */
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#define E1000_TCTL_EN 0x00000002 /* enable tx */
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#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
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#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
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#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
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#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
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#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
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#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
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#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
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#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
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#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
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/* Receive Descriptor */
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struct e1000_rx_desc {
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uint64_t buffer_addr; /* Address of the descriptor's data buffer */
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uint16_t length; /* Length of data DMAed into data buffer */
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uint16_t csum; /* Packet checksum */
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uint8_t status; /* Descriptor status */
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uint8_t errors; /* Descriptor Errors */
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uint16_t special;
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};
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2008-04-11 04:55:07 +00:00
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/* Receive Descriptor bit definitions */
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2008-02-03 02:20:18 +00:00
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#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
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#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
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#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
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#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
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#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
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#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
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#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
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#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
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#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
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#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
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#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
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#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
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#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
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#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
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#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
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#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
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#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
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#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
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#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
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#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
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#define E1000_RXD_SPC_PRI_SHIFT 13
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#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
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#define E1000_RXD_SPC_CFI_SHIFT 12
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#define E1000_RXDEXT_STATERR_CE 0x01000000
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#define E1000_RXDEXT_STATERR_SE 0x02000000
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#define E1000_RXDEXT_STATERR_SEQ 0x04000000
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#define E1000_RXDEXT_STATERR_CXE 0x10000000
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#define E1000_RXDEXT_STATERR_TCPE 0x20000000
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#define E1000_RXDEXT_STATERR_IPE 0x40000000
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#define E1000_RXDEXT_STATERR_RXE 0x80000000
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#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
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#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
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/* Receive Address */
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#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
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/* Offload Context Descriptor */
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struct e1000_context_desc {
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union {
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uint32_t ip_config;
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struct {
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uint8_t ipcss; /* IP checksum start */
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uint8_t ipcso; /* IP checksum offset */
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uint16_t ipcse; /* IP checksum end */
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} ip_fields;
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} lower_setup;
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union {
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uint32_t tcp_config;
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struct {
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uint8_t tucss; /* TCP checksum start */
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uint8_t tucso; /* TCP checksum offset */
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uint16_t tucse; /* TCP checksum end */
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} tcp_fields;
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} upper_setup;
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uint32_t cmd_and_length; /* */
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union {
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uint32_t data;
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struct {
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uint8_t status; /* Descriptor status */
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uint8_t hdr_len; /* Header length */
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uint16_t mss; /* Maximum segment size */
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} fields;
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} tcp_seg_setup;
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};
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/* Offload data descriptor */
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struct e1000_data_desc {
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uint64_t buffer_addr; /* Address of the descriptor's buffer address */
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union {
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uint32_t data;
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struct {
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uint16_t length; /* Data buffer length */
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uint8_t typ_len_ext; /* */
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uint8_t cmd; /* */
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} flags;
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} lower;
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union {
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uint32_t data;
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struct {
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uint8_t status; /* Descriptor status */
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uint8_t popts; /* Packet Options */
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uint16_t special; /* */
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} fields;
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} upper;
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};
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/* Management Control */
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#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
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#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
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#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
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#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
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#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
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#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
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#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
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#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
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#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
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#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
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* Filtering */
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#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
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#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
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#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
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#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
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#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
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#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
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#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
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* filtering */
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#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
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* memory */
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#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
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* filtering */
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#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
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#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
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#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
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#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
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#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
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#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
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#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
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#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
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#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
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#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
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/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
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#define EEPROM_SUM 0xBABA
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#endif /* _E1000_HW_H_ */
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