2007-04-30 01:26:42 +00:00
|
|
|
/*
|
|
|
|
* Intel XScale PXA Programmable Interrupt Controller.
|
|
|
|
*
|
|
|
|
* Copyright (c) 2006 Openedhand Ltd.
|
|
|
|
* Copyright (c) 2006 Thorsten Zitterell
|
|
|
|
* Written by Andrzej Zaborowski <balrog@zabor.org>
|
|
|
|
*
|
2011-06-26 02:21:35 +00:00
|
|
|
* This code is licensed under the GPL.
|
2007-04-30 01:26:42 +00:00
|
|
|
*/
|
|
|
|
|
2015-12-07 16:23:45 +00:00
|
|
|
#include "qemu/osdep.h"
|
qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 05:31:58 +00:00
|
|
|
#include "qapi/error.h"
|
2019-05-23 14:35:07 +00:00
|
|
|
#include "qemu/module.h"
|
2020-07-03 15:59:45 +00:00
|
|
|
#include "qemu/log.h"
|
2016-01-19 20:51:44 +00:00
|
|
|
#include "cpu.h"
|
2013-02-05 16:06:20 +00:00
|
|
|
#include "hw/arm/pxa.h"
|
2013-02-04 14:40:22 +00:00
|
|
|
#include "hw/sysbus.h"
|
2019-08-12 05:23:45 +00:00
|
|
|
#include "migration/vmstate.h"
|
2007-04-30 01:26:42 +00:00
|
|
|
|
|
|
|
#define ICIP 0x00 /* Interrupt Controller IRQ Pending register */
|
|
|
|
#define ICMR 0x04 /* Interrupt Controller Mask register */
|
|
|
|
#define ICLR 0x08 /* Interrupt Controller Level register */
|
|
|
|
#define ICFP 0x0c /* Interrupt Controller FIQ Pending register */
|
|
|
|
#define ICPR 0x10 /* Interrupt Controller Pending register */
|
|
|
|
#define ICCR 0x14 /* Interrupt Controller Control register */
|
|
|
|
#define ICHP 0x18 /* Interrupt Controller Highest Priority register */
|
|
|
|
#define IPR0 0x1c /* Interrupt Controller Priority register 0 */
|
|
|
|
#define IPR31 0x98 /* Interrupt Controller Priority register 31 */
|
|
|
|
#define ICIP2 0x9c /* Interrupt Controller IRQ Pending register 2 */
|
|
|
|
#define ICMR2 0xa0 /* Interrupt Controller Mask register 2 */
|
|
|
|
#define ICLR2 0xa4 /* Interrupt Controller Level register 2 */
|
|
|
|
#define ICFP2 0xa8 /* Interrupt Controller FIQ Pending register 2 */
|
|
|
|
#define ICPR2 0xac /* Interrupt Controller Pending register 2 */
|
|
|
|
#define IPR32 0xb0 /* Interrupt Controller Priority register 32 */
|
|
|
|
#define IPR39 0xcc /* Interrupt Controller Priority register 39 */
|
|
|
|
|
|
|
|
#define PXA2XX_PIC_SRCS 40
|
|
|
|
|
2013-07-24 00:08:09 +00:00
|
|
|
#define TYPE_PXA2XX_PIC "pxa2xx_pic"
|
|
|
|
#define PXA2XX_PIC(obj) \
|
|
|
|
OBJECT_CHECK(PXA2xxPICState, (obj), TYPE_PXA2XX_PIC)
|
|
|
|
|
2009-05-10 00:44:56 +00:00
|
|
|
typedef struct {
|
2013-07-24 00:08:09 +00:00
|
|
|
/*< private >*/
|
|
|
|
SysBusDevice parent_obj;
|
|
|
|
/*< public >*/
|
|
|
|
|
2011-10-30 13:50:17 +00:00
|
|
|
MemoryRegion iomem;
|
2012-05-03 22:05:29 +00:00
|
|
|
ARMCPU *cpu;
|
2007-04-30 01:26:42 +00:00
|
|
|
uint32_t int_enabled[2];
|
|
|
|
uint32_t int_pending[2];
|
|
|
|
uint32_t is_fiq[2];
|
|
|
|
uint32_t int_idle;
|
|
|
|
uint32_t priority[PXA2XX_PIC_SRCS];
|
2009-05-10 00:44:56 +00:00
|
|
|
} PXA2xxPICState;
|
2007-04-30 01:26:42 +00:00
|
|
|
|
|
|
|
static void pxa2xx_pic_update(void *opaque)
|
|
|
|
{
|
|
|
|
uint32_t mask[2];
|
2009-05-10 00:44:56 +00:00
|
|
|
PXA2xxPICState *s = (PXA2xxPICState *) opaque;
|
2013-01-17 17:51:17 +00:00
|
|
|
CPUState *cpu = CPU(s->cpu);
|
2007-04-30 01:26:42 +00:00
|
|
|
|
2013-01-17 17:51:17 +00:00
|
|
|
if (cpu->halted) {
|
2007-04-30 01:26:42 +00:00
|
|
|
mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
|
|
|
|
mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
|
2012-05-03 22:05:29 +00:00
|
|
|
if (mask[0] || mask[1]) {
|
2013-01-18 14:03:43 +00:00
|
|
|
cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
|
2012-05-03 22:05:29 +00:00
|
|
|
}
|
2007-04-30 01:26:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
mask[0] = s->int_pending[0] & s->int_enabled[0];
|
|
|
|
mask[1] = s->int_pending[1] & s->int_enabled[1];
|
|
|
|
|
2012-05-03 22:05:29 +00:00
|
|
|
if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
|
2013-01-18 14:03:43 +00:00
|
|
|
cpu_interrupt(cpu, CPU_INTERRUPT_FIQ);
|
2012-05-03 22:05:29 +00:00
|
|
|
} else {
|
2013-01-17 21:30:20 +00:00
|
|
|
cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ);
|
2012-05-03 22:05:29 +00:00
|
|
|
}
|
2007-04-30 01:26:42 +00:00
|
|
|
|
2012-05-03 22:05:29 +00:00
|
|
|
if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
|
2013-01-18 14:03:43 +00:00
|
|
|
cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
|
2012-05-03 22:05:29 +00:00
|
|
|
} else {
|
2013-01-17 21:30:20 +00:00
|
|
|
cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
|
2012-05-03 22:05:29 +00:00
|
|
|
}
|
2007-04-30 01:26:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Note: Here level means state of the signal on a pin, not
|
|
|
|
* IRQ/FIQ distinction as in PXA Developer Manual. */
|
|
|
|
static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
|
|
|
|
{
|
2009-05-10 00:44:56 +00:00
|
|
|
PXA2xxPICState *s = (PXA2xxPICState *) opaque;
|
2007-04-30 01:26:42 +00:00
|
|
|
int int_set = (irq >= 32);
|
|
|
|
irq &= 31;
|
|
|
|
|
|
|
|
if (level)
|
|
|
|
s->int_pending[int_set] |= 1 << irq;
|
|
|
|
else
|
|
|
|
s->int_pending[int_set] &= ~(1 << irq);
|
|
|
|
|
|
|
|
pxa2xx_pic_update(opaque);
|
|
|
|
}
|
|
|
|
|
2009-05-10 00:44:56 +00:00
|
|
|
static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
|
2007-04-30 01:26:42 +00:00
|
|
|
int i, int_set, irq;
|
|
|
|
uint32_t bit, mask[2];
|
|
|
|
uint32_t ichp = 0x003f003f; /* Both IDs invalid */
|
|
|
|
|
|
|
|
mask[0] = s->int_pending[0] & s->int_enabled[0];
|
|
|
|
mask[1] = s->int_pending[1] & s->int_enabled[1];
|
|
|
|
|
|
|
|
for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
|
|
|
|
irq = s->priority[i] & 0x3f;
|
2014-03-10 14:56:29 +00:00
|
|
|
if ((s->priority[i] & (1U << 31)) && irq < PXA2XX_PIC_SRCS) {
|
2007-04-30 01:26:42 +00:00
|
|
|
/* Source peripheral ID is valid. */
|
|
|
|
bit = 1 << (irq & 31);
|
|
|
|
int_set = (irq >= 32);
|
|
|
|
|
|
|
|
if (mask[int_set] & bit & s->is_fiq[int_set]) {
|
|
|
|
/* FIQ asserted */
|
|
|
|
ichp &= 0xffff0000;
|
|
|
|
ichp |= (1 << 15) | irq;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
|
|
|
|
/* IRQ asserted */
|
|
|
|
ichp &= 0x0000ffff;
|
2014-03-10 14:56:29 +00:00
|
|
|
ichp |= (1U << 31) | (irq << 16);
|
2007-04-30 01:26:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ichp;
|
|
|
|
}
|
|
|
|
|
2012-10-23 10:30:10 +00:00
|
|
|
static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
|
2011-10-30 13:50:17 +00:00
|
|
|
unsigned size)
|
2007-04-30 01:26:42 +00:00
|
|
|
{
|
2009-05-10 00:44:56 +00:00
|
|
|
PXA2xxPICState *s = (PXA2xxPICState *) opaque;
|
2007-04-30 01:26:42 +00:00
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case ICIP: /* IRQ Pending register */
|
|
|
|
return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
|
|
|
|
case ICIP2: /* IRQ Pending register 2 */
|
|
|
|
return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
|
|
|
|
case ICMR: /* Mask register */
|
|
|
|
return s->int_enabled[0];
|
|
|
|
case ICMR2: /* Mask register 2 */
|
|
|
|
return s->int_enabled[1];
|
|
|
|
case ICLR: /* Level register */
|
|
|
|
return s->is_fiq[0];
|
|
|
|
case ICLR2: /* Level register 2 */
|
|
|
|
return s->is_fiq[1];
|
|
|
|
case ICCR: /* Idle mask */
|
|
|
|
return (s->int_idle == 0);
|
|
|
|
case ICFP: /* FIQ Pending register */
|
|
|
|
return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
|
|
|
|
case ICFP2: /* FIQ Pending register 2 */
|
|
|
|
return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
|
|
|
|
case ICPR: /* Pending register */
|
|
|
|
return s->int_pending[0];
|
|
|
|
case ICPR2: /* Pending register 2 */
|
|
|
|
return s->int_pending[1];
|
|
|
|
case IPR0 ... IPR31:
|
|
|
|
return s->priority[0 + ((offset - IPR0 ) >> 2)];
|
|
|
|
case IPR32 ... IPR39:
|
|
|
|
return s->priority[32 + ((offset - IPR32) >> 2)];
|
|
|
|
case ICHP: /* Highest Priority register */
|
|
|
|
return pxa2xx_pic_highest(s);
|
|
|
|
default:
|
2020-07-03 15:59:45 +00:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx
|
|
|
|
"\n", offset);
|
2007-04-30 01:26:42 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 10:30:10 +00:00
|
|
|
static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
|
2011-10-30 13:50:17 +00:00
|
|
|
uint64_t value, unsigned size)
|
2007-04-30 01:26:42 +00:00
|
|
|
{
|
2009-05-10 00:44:56 +00:00
|
|
|
PXA2xxPICState *s = (PXA2xxPICState *) opaque;
|
2007-04-30 01:26:42 +00:00
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case ICMR: /* Mask register */
|
|
|
|
s->int_enabled[0] = value;
|
|
|
|
break;
|
|
|
|
case ICMR2: /* Mask register 2 */
|
|
|
|
s->int_enabled[1] = value;
|
|
|
|
break;
|
|
|
|
case ICLR: /* Level register */
|
|
|
|
s->is_fiq[0] = value;
|
|
|
|
break;
|
|
|
|
case ICLR2: /* Level register 2 */
|
|
|
|
s->is_fiq[1] = value;
|
|
|
|
break;
|
|
|
|
case ICCR: /* Idle mask */
|
|
|
|
s->int_idle = (value & 1) ? 0 : ~0;
|
|
|
|
break;
|
|
|
|
case IPR0 ... IPR31:
|
|
|
|
s->priority[0 + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
|
|
|
|
break;
|
|
|
|
case IPR32 ... IPR39:
|
|
|
|
s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
|
|
|
|
break;
|
|
|
|
default:
|
2020-07-03 15:59:45 +00:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"pxa2xx_pic_mem_write: bad register offset 0x%"
|
|
|
|
HWADDR_PRIx "\n", offset);
|
2007-04-30 01:26:42 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
pxa2xx_pic_update(opaque);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Interrupt Controller Coprocessor Space Register Mapping */
|
|
|
|
static const int pxa2xx_cp_reg_map[0x10] = {
|
|
|
|
[0x0 ... 0xf] = -1,
|
|
|
|
[0x0] = ICIP,
|
|
|
|
[0x1] = ICMR,
|
|
|
|
[0x2] = ICLR,
|
|
|
|
[0x3] = ICFP,
|
|
|
|
[0x4] = ICPR,
|
|
|
|
[0x5] = ICHP,
|
|
|
|
[0x6] = ICIP2,
|
|
|
|
[0x7] = ICMR2,
|
|
|
|
[0x8] = ICLR2,
|
|
|
|
[0x9] = ICFP2,
|
|
|
|
[0xa] = ICPR2,
|
|
|
|
};
|
|
|
|
|
2014-02-20 10:35:54 +00:00
|
|
|
static uint64_t pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri)
|
2007-04-30 01:26:42 +00:00
|
|
|
{
|
2012-06-20 11:57:08 +00:00
|
|
|
int offset = pxa2xx_cp_reg_map[ri->crn];
|
2014-02-20 10:35:54 +00:00
|
|
|
return pxa2xx_pic_mem_read(ri->opaque, offset, 4);
|
2007-04-30 01:26:42 +00:00
|
|
|
}
|
|
|
|
|
2014-02-20 10:35:54 +00:00
|
|
|
static void pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
|
|
|
uint64_t value)
|
2007-04-30 01:26:42 +00:00
|
|
|
{
|
2012-06-20 11:57:08 +00:00
|
|
|
int offset = pxa2xx_cp_reg_map[ri->crn];
|
|
|
|
pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
|
2007-04-30 01:26:42 +00:00
|
|
|
}
|
|
|
|
|
2012-06-20 11:57:08 +00:00
|
|
|
#define REGINFO_FOR_PIC_CP(NAME, CRN) \
|
|
|
|
{ .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
|
2015-06-15 17:06:09 +00:00
|
|
|
.access = PL1_RW, .type = ARM_CP_IO, \
|
2012-06-20 11:57:08 +00:00
|
|
|
.readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }
|
|
|
|
|
|
|
|
static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
|
|
|
|
REGINFO_FOR_PIC_CP("ICIP", 0),
|
|
|
|
REGINFO_FOR_PIC_CP("ICMR", 1),
|
|
|
|
REGINFO_FOR_PIC_CP("ICLR", 2),
|
|
|
|
REGINFO_FOR_PIC_CP("ICFP", 3),
|
|
|
|
REGINFO_FOR_PIC_CP("ICPR", 4),
|
|
|
|
REGINFO_FOR_PIC_CP("ICHP", 5),
|
|
|
|
REGINFO_FOR_PIC_CP("ICIP2", 6),
|
|
|
|
REGINFO_FOR_PIC_CP("ICMR2", 7),
|
|
|
|
REGINFO_FOR_PIC_CP("ICLR2", 8),
|
|
|
|
REGINFO_FOR_PIC_CP("ICFP2", 9),
|
|
|
|
REGINFO_FOR_PIC_CP("ICPR2", 0xa),
|
|
|
|
REGINFO_SENTINEL
|
|
|
|
};
|
|
|
|
|
2011-10-30 13:50:17 +00:00
|
|
|
static const MemoryRegionOps pxa2xx_pic_ops = {
|
|
|
|
.read = pxa2xx_pic_mem_read,
|
|
|
|
.write = pxa2xx_pic_mem_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2007-04-30 01:26:42 +00:00
|
|
|
};
|
|
|
|
|
2011-02-25 11:13:38 +00:00
|
|
|
static int pxa2xx_pic_post_load(void *opaque, int version_id)
|
2007-05-24 18:50:09 +00:00
|
|
|
{
|
|
|
|
pxa2xx_pic_update(opaque);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-23 10:30:10 +00:00
|
|
|
DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
|
2007-04-30 01:26:42 +00:00
|
|
|
{
|
qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 05:31:58 +00:00
|
|
|
DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC);
|
2013-07-24 00:08:09 +00:00
|
|
|
PXA2xxPICState *s = PXA2XX_PIC(dev);
|
2007-04-30 01:26:42 +00:00
|
|
|
|
2012-05-03 22:05:29 +00:00
|
|
|
s->cpu = cpu;
|
2007-04-30 01:26:42 +00:00
|
|
|
|
|
|
|
s->int_pending[0] = 0;
|
|
|
|
s->int_pending[1] = 0;
|
|
|
|
s->int_enabled[0] = 0;
|
|
|
|
s->int_enabled[1] = 0;
|
|
|
|
s->is_fiq[0] = 0;
|
|
|
|
s->is_fiq[1] = 0;
|
|
|
|
|
sysbus: Convert to sysbus_realize() etc. with Coccinelle
Convert from qdev_realize(), qdev_realize_and_unref() with null @bus
argument to sysbus_realize(), sysbus_realize_and_unref().
Coccinelle script:
@@
expression dev, errp;
@@
- qdev_realize(DEVICE(dev), NULL, errp);
+ sysbus_realize(SYS_BUS_DEVICE(dev), errp);
@@
expression sysbus_dev, dev, errp;
@@
+ sysbus_dev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
- sysbus_dev = SYS_BUS_DEVICE(dev);
@@
expression sysbus_dev, dev, errp;
expression expr;
@@
sysbus_dev = SYS_BUS_DEVICE(dev);
... when != dev = expr;
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(DEVICE(dev), NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
Whitespace changes minimized manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-46-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 05:32:34 +00:00
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
2011-02-25 11:13:38 +00:00
|
|
|
|
|
|
|
qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
|
2007-04-30 01:26:42 +00:00
|
|
|
|
|
|
|
/* Enable IC memory-mapped registers access. */
|
2013-06-07 01:25:08 +00:00
|
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_pic_ops, s,
|
2011-10-30 13:50:17 +00:00
|
|
|
"pxa2xx-pic", 0x00100000);
|
2013-01-20 01:47:33 +00:00
|
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
|
2007-04-30 01:26:42 +00:00
|
|
|
|
|
|
|
/* Enable IC coprocessor access. */
|
2013-07-24 00:08:09 +00:00
|
|
|
define_arm_cp_regs_with_opaque(cpu, pxa_pic_cp_reginfo, s);
|
2007-04-30 01:26:42 +00:00
|
|
|
|
2011-02-25 11:13:38 +00:00
|
|
|
return dev;
|
|
|
|
}
|
|
|
|
|
|
|
|
static VMStateDescription vmstate_pxa2xx_pic_regs = {
|
|
|
|
.name = "pxa2xx_pic",
|
|
|
|
.version_id = 0,
|
|
|
|
.minimum_version_id = 0,
|
|
|
|
.post_load = pxa2xx_pic_post_load,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
|
|
|
|
VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
|
|
|
|
VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
|
|
|
|
VMSTATE_UINT32(int_idle, PXA2xxPICState),
|
|
|
|
VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
|
|
|
|
VMSTATE_END_OF_LIST(),
|
|
|
|
},
|
|
|
|
};
|
2007-05-24 18:50:09 +00:00
|
|
|
|
2012-01-24 19:12:29 +00:00
|
|
|
static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 03:34:16 +00:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 19:12:29 +00:00
|
|
|
|
2011-12-08 03:34:16 +00:00
|
|
|
dc->desc = "PXA2xx PIC";
|
|
|
|
dc->vmsd = &vmstate_pxa2xx_pic_regs;
|
2012-01-24 19:12:29 +00:00
|
|
|
}
|
|
|
|
|
2013-01-10 15:19:07 +00:00
|
|
|
static const TypeInfo pxa2xx_pic_info = {
|
2013-07-24 00:08:09 +00:00
|
|
|
.name = TYPE_PXA2XX_PIC,
|
2011-12-08 03:34:16 +00:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(PXA2xxPICState),
|
|
|
|
.class_init = pxa2xx_pic_class_init,
|
2011-02-25 11:13:38 +00:00
|
|
|
};
|
|
|
|
|
2012-02-09 14:20:55 +00:00
|
|
|
static void pxa2xx_pic_register_types(void)
|
2011-02-25 11:13:38 +00:00
|
|
|
{
|
2011-12-08 03:34:16 +00:00
|
|
|
type_register_static(&pxa2xx_pic_info);
|
2007-04-30 01:26:42 +00:00
|
|
|
}
|
2012-02-09 14:20:55 +00:00
|
|
|
|
|
|
|
type_init(pxa2xx_pic_register_types)
|