2020-09-12 17:47:33 +00:00
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/*
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* Interface to the capstone disassembler.
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/bswap.h"
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#include "disas/dis-asm.h"
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#include "disas/capstone.h"
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/*
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* Temporary storage for the capstone library. This will be alloced via
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* malloc with a size private to the library; thus there's no reason not
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* to share this across calls and across host vs target disassembly.
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*/
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static __thread cs_insn *cap_insn;
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2020-09-12 01:19:41 +00:00
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/*
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* The capstone library always skips 2 bytes for S390X.
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* This is less than ideal, since we can tell from the first two bits
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* the size of the insn and thus stay in sync with the insn stream.
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*/
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static size_t CAPSTONE_API
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cap_skipdata_s390x_cb(const uint8_t *code, size_t code_size,
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size_t offset, void *user_data)
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{
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size_t ilen;
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/* See get_ilen() in target/s390x/internal.h. */
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switch (code[offset] >> 6) {
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case 0:
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ilen = 2;
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break;
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case 1:
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case 2:
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ilen = 4;
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break;
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default:
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ilen = 6;
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break;
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}
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return ilen;
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}
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static const cs_opt_skipdata cap_skipdata_s390x = {
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.mnemonic = ".byte",
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.callback = cap_skipdata_s390x_cb
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};
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2020-09-12 17:47:33 +00:00
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/*
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* Initialize the Capstone library.
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*
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* ??? It would be nice to cache this. We would need one handle for the
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* host and one for the target. For most targets we can reset specific
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* parameters via cs_option(CS_OPT_MODE, new_mode), but we cannot change
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* CS_ARCH_* in this way. Thus we would need to be able to close and
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* re-open the target handle with a different arch for the target in order
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* to handle AArch64 vs AArch32 mode switching.
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*/
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static cs_err cap_disas_start(disassemble_info *info, csh *handle)
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{
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cs_mode cap_mode = info->cap_mode;
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cs_err err;
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cap_mode += (info->endian == BFD_ENDIAN_BIG ? CS_MODE_BIG_ENDIAN
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: CS_MODE_LITTLE_ENDIAN);
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err = cs_open(info->cap_arch, cap_mode, handle);
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if (err != CS_ERR_OK) {
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return err;
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}
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/* "Disassemble" unknown insns as ".byte W,X,Y,Z". */
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cs_option(*handle, CS_OPT_SKIPDATA, CS_OPT_ON);
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2020-09-12 01:19:41 +00:00
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switch (info->cap_arch) {
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case CS_ARCH_SYSZ:
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cs_option(*handle, CS_OPT_SKIPDATA_SETUP,
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(uintptr_t)&cap_skipdata_s390x);
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break;
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case CS_ARCH_X86:
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2020-09-12 17:47:33 +00:00
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/*
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* We don't care about errors (if for some reason the library
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* is compiled without AT&T syntax); the user will just have
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* to deal with the Intel syntax.
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*/
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cs_option(*handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT);
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2020-09-12 01:19:41 +00:00
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break;
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2020-09-12 17:47:33 +00:00
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}
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/* Allocate temp space for cs_disasm_iter. */
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if (cap_insn == NULL) {
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cap_insn = cs_malloc(*handle);
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if (cap_insn == NULL) {
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cs_close(handle);
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return CS_ERR_MEM;
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}
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}
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return CS_ERR_OK;
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}
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static void cap_dump_insn_units(disassemble_info *info, cs_insn *insn,
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int i, int n)
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{
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fprintf_function print = info->fprintf_func;
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FILE *stream = info->stream;
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switch (info->cap_insn_unit) {
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case 4:
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if (info->endian == BFD_ENDIAN_BIG) {
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for (; i < n; i += 4) {
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print(stream, " %08x", ldl_be_p(insn->bytes + i));
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}
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} else {
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for (; i < n; i += 4) {
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print(stream, " %08x", ldl_le_p(insn->bytes + i));
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}
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}
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break;
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case 2:
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if (info->endian == BFD_ENDIAN_BIG) {
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for (; i < n; i += 2) {
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print(stream, " %04x", lduw_be_p(insn->bytes + i));
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}
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} else {
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for (; i < n; i += 2) {
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print(stream, " %04x", lduw_le_p(insn->bytes + i));
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}
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}
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break;
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default:
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for (; i < n; i++) {
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print(stream, " %02x", insn->bytes[i]);
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}
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break;
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}
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}
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static void cap_dump_insn(disassemble_info *info, cs_insn *insn)
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{
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fprintf_function print = info->fprintf_func;
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FILE *stream = info->stream;
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int i, n, split;
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print(stream, "0x%08" PRIx64 ": ", insn->address);
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n = insn->size;
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split = info->cap_insn_split;
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/* Dump the first SPLIT bytes of the instruction. */
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cap_dump_insn_units(info, insn, 0, MIN(n, split));
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/* Add padding up to SPLIT so that mnemonics line up. */
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if (n < split) {
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int width = (split - n) / info->cap_insn_unit;
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width *= (2 * info->cap_insn_unit + 1);
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print(stream, "%*s", width, "");
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}
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/* Print the actual instruction. */
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print(stream, " %-8s %s\n", insn->mnemonic, insn->op_str);
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/* Dump any remaining part of the insn on subsequent lines. */
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for (i = split; i < n; i += split) {
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print(stream, "0x%08" PRIx64 ": ", insn->address + i);
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cap_dump_insn_units(info, insn, i, MIN(n, i + split));
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print(stream, "\n");
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}
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}
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/* Disassemble SIZE bytes at PC for the target. */
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bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size)
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{
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uint8_t cap_buf[1024];
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csh handle;
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cs_insn *insn;
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size_t csize = 0;
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if (cap_disas_start(info, &handle) != CS_ERR_OK) {
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return false;
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}
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insn = cap_insn;
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while (1) {
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size_t tsize = MIN(sizeof(cap_buf) - csize, size);
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const uint8_t *cbuf = cap_buf;
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info->read_memory_func(pc + csize, cap_buf + csize, tsize, info);
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csize += tsize;
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size -= tsize;
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while (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) {
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cap_dump_insn(info, insn);
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}
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/* If the target memory is not consumed, go back for more... */
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if (size != 0) {
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/*
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* ... taking care to move any remaining fractional insn
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* to the beginning of the buffer.
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*/
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if (csize != 0) {
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memmove(cap_buf, cbuf, csize);
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}
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continue;
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}
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/*
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* Since the target memory is consumed, we should not have
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* a remaining fractional insn.
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*/
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if (csize != 0) {
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info->fprintf_func(info->stream,
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"Disassembler disagrees with translator "
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"over instruction decoding\n"
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"Please report this to qemu-devel@nongnu.org\n");
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}
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break;
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}
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cs_close(&handle);
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return true;
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}
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/* Disassemble SIZE bytes at CODE for the host. */
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2020-10-31 03:59:01 +00:00
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bool cap_disas_host(disassemble_info *info, const void *code, size_t size)
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2020-09-12 17:47:33 +00:00
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{
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csh handle;
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const uint8_t *cbuf;
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cs_insn *insn;
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uint64_t pc;
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if (cap_disas_start(info, &handle) != CS_ERR_OK) {
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return false;
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}
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insn = cap_insn;
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cbuf = code;
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pc = (uintptr_t)code;
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while (cs_disasm_iter(handle, &cbuf, &size, &pc, insn)) {
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cap_dump_insn(info, insn);
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}
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if (size != 0) {
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info->fprintf_func(info->stream,
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"Disassembler disagrees with TCG over instruction encoding\n"
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"Please report this to qemu-devel@nongnu.org\n");
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}
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cs_close(&handle);
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return true;
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}
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/* Disassemble COUNT insns at PC for the target. */
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bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count)
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{
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uint8_t cap_buf[32];
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csh handle;
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cs_insn *insn;
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size_t csize = 0;
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if (cap_disas_start(info, &handle) != CS_ERR_OK) {
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return false;
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}
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insn = cap_insn;
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while (1) {
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/*
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* We want to read memory for one insn, but generically we do not
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* know how much memory that is. We have a small buffer which is
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* known to be sufficient for all supported targets. Try to not
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* read beyond the page, Just In Case. For even more simplicity,
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* ignore the actual target page size and use a 1k boundary. If
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* that turns out to be insufficient, we'll come back around the
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* loop and read more.
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*/
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uint64_t epc = QEMU_ALIGN_UP(pc + csize + 1, 1024);
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size_t tsize = MIN(sizeof(cap_buf) - csize, epc - pc);
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const uint8_t *cbuf = cap_buf;
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/* Make certain that we can make progress. */
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assert(tsize != 0);
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disas/capstone: Fix monitor disassembly of >32 bytes
If we're using the capstone disassembler, disassembly of a run of
instructions more than 32 bytes long disassembles the wrong data for
instructions beyond the 32 byte mark:
(qemu) xp /16x 0x100
0000000000000100: 0x00000005 0x54410001 0x00000001 0x00001000
0000000000000110: 0x00000000 0x00000004 0x54410002 0x3c000000
0000000000000120: 0x00000000 0x00000004 0x54410009 0x74736574
0000000000000130: 0x00000000 0x00000000 0x00000000 0x00000000
(qemu) xp /16i 0x100
0x00000100: 00000005 andeq r0, r0, r5
0x00000104: 54410001 strbpl r0, [r1], #-1
0x00000108: 00000001 andeq r0, r0, r1
0x0000010c: 00001000 andeq r1, r0, r0
0x00000110: 00000000 andeq r0, r0, r0
0x00000114: 00000004 andeq r0, r0, r4
0x00000118: 54410002 strbpl r0, [r1], #-2
0x0000011c: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c
0x00000120: 54410001 strbpl r0, [r1], #-1
0x00000124: 00000001 andeq r0, r0, r1
0x00000128: 00001000 andeq r1, r0, r0
0x0000012c: 00000000 andeq r0, r0, r0
0x00000130: 00000004 andeq r0, r0, r4
0x00000134: 54410002 strbpl r0, [r1], #-2
0x00000138: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c
0x0000013c: 00000000 andeq r0, r0, r0
Here the disassembly of 0x120..0x13f is using the data that is in
0x104..0x123.
This is caused by passing the wrong value to the read_memory_func().
The intention is that at this point in the loop the 'cap_buf' buffer
already contains 'csize' bytes of data for the instruction at guest
addr 'pc', and we want to read in an extra 'tsize' bytes. Those
extra bytes are therefore at 'pc + csize', not 'pc'. On the first
time through the loop 'csize' happens to be zero, so the initial read
of 32 bytes into cap_buf is correct and as long as the disassembly
never needs to read more data we return the correct information.
Use the correct guest address in the call to read_memory_func().
Cc: qemu-stable@nongnu.org
Fixes: https://bugs.launchpad.net/qemu/+bug/1900779
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201022132445.25039-1-peter.maydell@linaro.org
2020-11-02 16:52:16 +00:00
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info->read_memory_func(pc + csize, cap_buf + csize, tsize, info);
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2020-09-12 17:47:33 +00:00
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csize += tsize;
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if (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) {
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cap_dump_insn(info, insn);
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if (--count <= 0) {
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break;
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}
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}
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memmove(cap_buf, cbuf, csize);
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}
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cs_close(&handle);
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return true;
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}
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/* Disassemble a single instruction directly into plugin output */
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bool cap_disas_plugin(disassemble_info *info, uint64_t pc, size_t size)
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{
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uint8_t cap_buf[32];
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const uint8_t *cbuf = cap_buf;
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csh handle;
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if (cap_disas_start(info, &handle) != CS_ERR_OK) {
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return false;
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}
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assert(size < sizeof(cap_buf));
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info->read_memory_func(pc, cap_buf, size, info);
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if (cs_disasm_iter(handle, &cbuf, &size, &pc, cap_insn)) {
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info->fprintf_func(info->stream, "%s %s",
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cap_insn->mnemonic, cap_insn->op_str);
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}
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cs_close(&handle);
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return true;
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}
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