2018-05-04 17:05:51 +00:00
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/*
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* Copyright (C) 2014-2016 Broadcom Corporation
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* Copyright (c) 2017 Red Hat, Inc.
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* Written by Prem Mallappa, Eric Auger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Author: Prem Mallappa <pmallapp@broadcom.com>
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*
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*/
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#include "qemu/osdep.h"
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#include "sysemu/sysemu.h"
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#include "exec/address-spaces.h"
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#include "trace.h"
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#include "exec/target_page.h"
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#include "qom/cpu.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "hw/arm/smmu-common.h"
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2018-05-04 17:05:51 +00:00
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/**
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* The bus number is used for lookup when SID based invalidation occurs.
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* In that case we lazily populate the SMMUPciBus array from the bus hash
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* table. At the time the SMMUPciBus is created (smmu_find_add_as), the bus
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* numbers may not be always initialized yet.
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*/
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SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num)
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{
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SMMUPciBus *smmu_pci_bus = s->smmu_pcibus_by_bus_num[bus_num];
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if (!smmu_pci_bus) {
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GHashTableIter iter;
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g_hash_table_iter_init(&iter, s->smmu_pcibus_by_busptr);
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while (g_hash_table_iter_next(&iter, NULL, (void **)&smmu_pci_bus)) {
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if (pci_bus_num(smmu_pci_bus->bus) == bus_num) {
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s->smmu_pcibus_by_bus_num[bus_num] = smmu_pci_bus;
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return smmu_pci_bus;
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}
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}
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}
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return smmu_pci_bus;
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}
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static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
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{
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SMMUState *s = opaque;
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SMMUPciBus *sbus = g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus);
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SMMUDevice *sdev;
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if (!sbus) {
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sbus = g_malloc0(sizeof(SMMUPciBus) +
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sizeof(SMMUDevice *) * SMMU_PCI_DEVFN_MAX);
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sbus->bus = bus;
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g_hash_table_insert(s->smmu_pcibus_by_busptr, bus, sbus);
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}
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sdev = sbus->pbdev[devfn];
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if (!sdev) {
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char *name = g_strdup_printf("%s-%d-%d",
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s->mrtypename,
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pci_bus_num(bus), devfn);
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sdev = sbus->pbdev[devfn] = g_new0(SMMUDevice, 1);
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sdev->smmu = s;
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sdev->bus = bus;
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sdev->devfn = devfn;
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memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu),
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s->mrtypename,
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OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS);
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address_space_init(&sdev->as,
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MEMORY_REGION(&sdev->iommu), name);
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trace_smmu_add_mr(name);
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g_free(name);
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}
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return &sdev->as;
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}
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2018-05-04 17:05:51 +00:00
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static void smmu_base_realize(DeviceState *dev, Error **errp)
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{
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2018-05-04 17:05:51 +00:00
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SMMUState *s = ARM_SMMU(dev);
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2018-05-04 17:05:51 +00:00
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SMMUBaseClass *sbc = ARM_SMMU_GET_CLASS(dev);
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Error *local_err = NULL;
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sbc->parent_realize(dev, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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2018-05-04 17:05:51 +00:00
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s->smmu_pcibus_by_busptr = g_hash_table_new(NULL, NULL);
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if (s->primary_bus) {
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pci_setup_iommu(s->primary_bus, smmu_find_add_as, s);
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} else {
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error_setg(errp, "SMMU is not attached to any PCI bus!");
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}
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2018-05-04 17:05:51 +00:00
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}
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static void smmu_base_reset(DeviceState *dev)
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{
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/* will be filled later on */
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}
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static Property smmu_dev_properties[] = {
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DEFINE_PROP_UINT8("bus_num", SMMUState, bus_num, 0),
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DEFINE_PROP_LINK("primary-bus", SMMUState, primary_bus, "PCI", PCIBus *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void smmu_base_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass);
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dc->props = smmu_dev_properties;
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device_class_set_parent_realize(dc, smmu_base_realize,
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&sbc->parent_realize);
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dc->reset = smmu_base_reset;
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}
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static const TypeInfo smmu_base_info = {
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.name = TYPE_ARM_SMMU,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SMMUState),
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.class_data = NULL,
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.class_size = sizeof(SMMUBaseClass),
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.class_init = smmu_base_class_init,
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.abstract = true,
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};
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static void smmu_base_register_types(void)
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{
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type_register_static(&smmu_base_info);
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}
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type_init(smmu_base_register_types)
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