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pci, pc, virtio fixes and cleanups

Browse Source 
A bunch of fixes all over the place.
 All of ACPI refactoring has been merged.
 Legacy pci commands have been dropped.
 virtio header cleanup
 initial patches from virtio-1.0 branch
 
 Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging

pci, pc, virtio fixes and cleanups

A bunch of fixes all over the place.
All of ACPI refactoring has been merged.
Legacy pci commands have been dropped.
virtio header cleanup
initial patches from virtio-1.0 branch

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

* remotes/mst/tags/for_upstream: (130 commits)
  acpi: drop unused code
  aml-build: comment fix
  acpi-build: fix typo in comment
  acpi: update generated files
  vhost user:support vhost user nic for non msi guests
  aml-build: fix build for glib < 2.22
  acpi: update generated files
  Makefile.target: binary depends on config-devices
  acpi-test-data: update after pci rewrite
  acpi, mem-hotplug: use PC_DIMM_SLOT_PROP in acpi_memory_plug_cb().
  pci-hotplug-old: Has been dead for five major releases, bury
  pci: Give a few helpers internal linkage
  acpi: make build_*() routines static to aml-build.c
  pc: acpi: remove not used anymore ssdt-[misc|pcihp].hex.generated blobs
  pc: acpi-build: drop template patching and create PCI bus tree dynamically
  tests: ACPI: update pc/SSDT.bridge due to new alg of PCI tree creation
  pc: acpi-build: simplify PCI bus tree generation
  tests: add ACPI blobs for qemu with bridge cases
  tests: bios-tables-test: add support for testing bridges
  tests: ACPI test blobs update due to PCI0._CRS changes
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Conflicts:
	hw/pci/pci-hotplug-old.c
This commit is contained in:
Peter Maydell 2015-03-09 09:14:28 +00:00
commit 0048fa6c80
155 changed files with 3585 additions and 5287 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
default-configs/i386-softmmu.mak
View File

@ -26,7 +26,6 @@ CONFIG_APPLESMC=y
CONFIG_I8259=y
CONFIG_PFLASH_CFI01=y
CONFIG_TPM_TIS=$(CONFIG_TPM)
CONFIG_PCI_HOTPLUG_OLD=y
CONFIG_MC146818RTC=y
CONFIG_PAM=y
CONFIG_PCI_PIIX=y

1
default-configs/x86_64-softmmu.mak
View File

@ -26,7 +26,6 @@ CONFIG_APPLESMC=y
CONFIG_I8259=y
CONFIG_PFLASH_CFI01=y
CONFIG_TPM_TIS=$(CONFIG_TPM)
CONFIG_PCI_HOTPLUG_OLD=y
CONFIG_MC146818RTC=y
CONFIG_PAM=y
CONFIG_PCI_PIIX=y

7
device-hotplug.c
View File

@ -30,7 +30,7 @@
#include "sysemu/sysemu.h"
#include "monitor/monitor.h"
DriveInfo *add_init_drive(const char *optstr)
static DriveInfo *add_init_drive(const char *optstr)
{
DriveInfo *dinfo;
QemuOpts *opts;
@ -69,9 +69,8 @@ void hmp_drive_add(Monitor *mon, const QDict *qdict)
monitor_printf(mon, "OK\n");
break;
default:
if (pci_drive_hot_add(mon, qdict, dinfo)) {
goto err;
}
monitor_printf(mon, "Can't hot-add drive to type %d\n", dinfo->type);
goto err;
}
return;

2
exec.c
View File

@ -1347,6 +1347,8 @@ int qemu_ram_resize(ram_addr_t base, ram_addr_t newsize, Error **errp)
assert(block);
newsize = TARGET_PAGE_ALIGN(newsize);
if (block->used_length == newsize) {
return 0;
}

32
hmp-commands.hx
View File

@ -1147,38 +1147,6 @@ STEXI
@item drive_add
@findex drive_add
Add drive to PCI storage controller.
ETEXI
#if defined(CONFIG_PCI_HOTPLUG_OLD)
{
.name = "pci_add",
.args_type = "pci_addr:s,type:s,opts:s?",
.params = "auto|[[<domain>:]<bus>:]<slot> nic|storage [[vlan=n][,macaddr=addr][,model=type]] [file=file][,if=type][,bus=nr]...",
.help = "hot-add PCI device",
.mhandler.cmd = hmp_pci_add,
},
#endif
STEXI
@item pci_add
@findex pci_add
Hot-add PCI device.
ETEXI
#if defined(CONFIG_PCI_HOTPLUG_OLD)
{
.name = "pci_del",
.args_type = "pci_addr:s",
.params = "[[<domain>:]<bus>:]<slot>",
.help = "hot remove PCI device",
.mhandler.cmd = hmp_pci_del,
},
#endif
STEXI
@item pci_del
@findex pci_del
Hot remove PCI device.
ETEXI
{

2
hw/9pfs/virtio-9p-device.c
View File

@ -23,7 +23,7 @@
static uint32_t virtio_9p_get_features(VirtIODevice *vdev, uint32_t features)
{
features |= 1 << VIRTIO_9P_MOUNT_TAG;
virtio_add_feature(&features, VIRTIO_9P_MOUNT_TAG);
return features;
}

18
hw/9pfs/virtio-9p.h
View File

@ -7,16 +7,14 @@
#include <utime.h>
#include <sys/resource.h>
#include <glib.h>
#include "standard-headers/linux/virtio_9p.h"
#include "hw/virtio/virtio.h"
#include "hw/virtio/virtio-9p.h"
#include "fsdev/file-op-9p.h"
#include "fsdev/virtio-9p-marshal.h"
#include "qemu/thread.h"
#include "block/coroutine.h"
/* The feature bitmap for virtio 9P */
/* The mount point is specified in a config variable */
#define VIRTIO_9P_MOUNT_TAG 0
enum {
P9_TLERROR = 6,
P9_RLERROR,
@ -144,10 +142,6 @@ struct V9fsPDU
* 1) change user needs to set groups and stuff
*/
/* from Linux's linux/virtio_9p.h */
/* The ID for virtio console */
#define VIRTIO_ID_9P 9
#define MAX_REQ 128
#define MAX_TAG_LEN 32
@ -277,14 +271,6 @@ typedef struct V9fsWriteState {
int cnt;
} V9fsWriteState;
struct virtio_9p_config
{
/* number of characters in tag */
uint16_t tag_len;
/* Variable size tag name */
uint8_t tag[0];
} QEMU_PACKED;
typedef struct V9fsMkState {
V9fsPDU *pdu;
size_t offset;

1
hw/acpi/Makefile.objs
View File

@ -2,3 +2,4 @@ common-obj-$(CONFIG_ACPI) += core.o piix4.o ich9.o pcihp.o cpu_hotplug.o
common-obj-$(CONFIG_ACPI) += memory_hotplug.o
common-obj-$(CONFIG_ACPI) += acpi_interface.o
common-obj-$(CONFIG_ACPI) += bios-linker-loader.o
common-obj-$(CONFIG_ACPI) += aml-build.o

889
hw/acpi/aml-build.c Normal file
View File

@ -0,0 +1,889 @@
/* Support for generating ACPI tables and passing them to Guests
*
* Copyright (C) 2015 Red Hat Inc
*
* Author: Michael S. Tsirkin <mst@redhat.com>
* Author: Igor Mammedov <imammedo@redhat.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include <stdio.h>
#include <stdarg.h>
#include <assert.h>
#include <stdbool.h>
#include <string.h>
#include "hw/acpi/aml-build.h"
#include "qemu/bswap.h"
static GArray *build_alloc_array(void)
{
return g_array_new(false, true /* clear */, 1);
}
static void build_free_array(GArray *array)
{
g_array_free(array, true);
}
static void build_prepend_byte(GArray *array, uint8_t val)
{
g_array_prepend_val(array, val);
}
static void build_append_byte(GArray *array, uint8_t val)
{
g_array_append_val(array, val);
}
static void build_append_array(GArray *array, GArray *val)
{
g_array_append_vals(array, val->data, val->len);
}
#define ACPI_NAMESEG_LEN 4
static void
build_append_nameseg(GArray *array, const char *seg)
{
/* It would be nicer to use g_string_vprintf but it's only there in 2.22 */
int len;
len = strlen(seg);
assert(len <= ACPI_NAMESEG_LEN);
g_array_append_vals(array, seg, len);
/* Pad up to ACPI_NAMESEG_LEN characters if necessary. */
g_array_append_vals(array, "____", ACPI_NAMESEG_LEN - len);
}
static void
build_append_namestringv(GArray *array, const char *format, va_list ap)
{
/* It would be nicer to use g_string_vprintf but it's only there in 2.22 */
char *s;
int len;
va_list va_len;
char **segs;
char **segs_iter;
int seg_count = 0;
va_copy(va_len, ap);
len = vsnprintf(NULL, 0, format, va_len);
va_end(va_len);
len += 1;
s = g_new(typeof(*s), len);
len = vsnprintf(s, len, format, ap);
segs = g_strsplit(s, ".", 0);
g_free(s);
/* count segments */
segs_iter = segs;
while (*segs_iter) {
++segs_iter;
++seg_count;
}
/*
* ACPI 5.0 spec: 20.2.2 Name Objects Encoding:
* "SegCount can be from 1 to 255"
*/
assert(seg_count > 0 && seg_count <= 255);
/* handle RootPath || PrefixPath */
s = *segs;
while (*s == '\\' || *s == '^') {
build_append_byte(array, *s);
++s;
}
switch (seg_count) {
case 1:
if (!*s) {
build_append_byte(array, 0x0); /* NullName */
} else {
build_append_nameseg(array, s);
}
break;
case 2:
build_append_byte(array, 0x2E); /* DualNamePrefix */
build_append_nameseg(array, s);
build_append_nameseg(array, segs[1]);
break;
default:
build_append_byte(array, 0x2F); /* MultiNamePrefix */
build_append_byte(array, seg_count);
/* handle the 1st segment manually due to prefix/root path */
build_append_nameseg(array, s);
/* add the rest of segments */
segs_iter = segs + 1;
while (*segs_iter) {
build_append_nameseg(array, *segs_iter);
++segs_iter;
}
break;
}
g_strfreev(segs);
}
static void build_append_namestring(GArray *array, const char *format, ...)
{
va_list ap;
va_start(ap, format);
build_append_namestringv(array, format, ap);
va_end(ap);
}
/* 5.4 Definition Block Encoding */
enum {
PACKAGE_LENGTH_1BYTE_SHIFT = 6, /* Up to 63 - use extra 2 bits. */
PACKAGE_LENGTH_2BYTE_SHIFT = 4,
PACKAGE_LENGTH_3BYTE_SHIFT = 12,
PACKAGE_LENGTH_4BYTE_SHIFT = 20,
};
static void
build_prepend_package_length(GArray *package, unsigned length, bool incl_self)
{
uint8_t byte;
unsigned length_bytes;
if (length + 1 < (1 << PACKAGE_LENGTH_1BYTE_SHIFT)) {
length_bytes = 1;
} else if (length + 2 < (1 << PACKAGE_LENGTH_3BYTE_SHIFT)) {
length_bytes = 2;
} else if (length + 3 < (1 << PACKAGE_LENGTH_4BYTE_SHIFT)) {
length_bytes = 3;
} else {
length_bytes = 4;
}
/*
* NamedField uses PkgLength encoding but it doesn't include length
* of PkgLength itself.
*/
if (incl_self) {
/*
* PkgLength is the length of the inclusive length of the data
* and PkgLength's length itself when used for terms with
* explitit length.
*/
length += length_bytes;
}
switch (length_bytes) {
case 1:
byte = length;
build_prepend_byte(package, byte);
return;
case 4:
byte = length >> PACKAGE_LENGTH_4BYTE_SHIFT;
build_prepend_byte(package, byte);
length &= (1 << PACKAGE_LENGTH_4BYTE_SHIFT) - 1;
/* fall through */
case 3:
byte = length >> PACKAGE_LENGTH_3BYTE_SHIFT;
build_prepend_byte(package, byte);
length &= (1 << PACKAGE_LENGTH_3BYTE_SHIFT) - 1;
/* fall through */
case 2:
byte = length >> PACKAGE_LENGTH_2BYTE_SHIFT;
build_prepend_byte(package, byte);
length &= (1 << PACKAGE_LENGTH_2BYTE_SHIFT) - 1;
/* fall through */
}
/*
* Most significant two bits of byte zero indicate how many following bytes
* are in PkgLength encoding.
*/
byte = ((length_bytes - 1) << PACKAGE_LENGTH_1BYTE_SHIFT) | length;
build_prepend_byte(package, byte);
}
static void
build_append_pkg_length(GArray *array, unsigned length, bool incl_self)
{
GArray *tmp = build_alloc_array();
build_prepend_package_length(tmp, length, incl_self);
build_append_array(array, tmp);
build_free_array(tmp);
}
static void build_package(GArray *package, uint8_t op)
{
build_prepend_package_length(package, package->len, true);
build_prepend_byte(package, op);
}
static void build_extop_package(GArray *package, uint8_t op)
{
build_package(package, op);
build_prepend_byte(package, 0x5B); /* ExtOpPrefix */
}
static void build_append_int_noprefix(GArray *table, uint64_t value, int size)
{
int i;
for (i = 0; i < size; ++i) {
build_append_byte(table, value & 0xFF);
value = value >> 8;
}
}
static void build_append_int(GArray *table, uint64_t value)
{
if (value == 0x00) {
build_append_byte(table, 0x00); /* ZeroOp */
} else if (value == 0x01) {
build_append_byte(table, 0x01); /* OneOp */
} else if (value <= 0xFF) {
build_append_byte(table, 0x0A); /* BytePrefix */
build_append_int_noprefix(table, value, 1);
} else if (value <= 0xFFFF) {
build_append_byte(table, 0x0B); /* WordPrefix */
build_append_int_noprefix(table, value, 2);
} else if (value <= 0xFFFFFFFF) {
build_append_byte(table, 0x0C); /* DWordPrefix */
build_append_int_noprefix(table, value, 4);
} else {
build_append_byte(table, 0x0E); /* QWordPrefix */
build_append_int_noprefix(table, value, 8);
}
}
static GPtrArray *alloc_list;
static Aml *aml_alloc(void)
{
Aml *var = g_new0(typeof(*var), 1);
g_ptr_array_add(alloc_list, var);
var->block_flags = AML_NO_OPCODE;
var->buf = build_alloc_array();
return var;
}
static Aml *aml_opcode(uint8_t op)
{
Aml *var = aml_alloc();
var->op = op;
var->block_flags = AML_OPCODE;
return var;
}
static Aml *aml_bundle(uint8_t op, AmlBlockFlags flags)
{
Aml *var = aml_alloc();
var->op = op;
var->block_flags = flags;
return var;
}
static void aml_free(gpointer data, gpointer user_data)
{
Aml *var = data;
build_free_array(var->buf);
}
Aml *init_aml_allocator(void)
{
Aml *var;
assert(!alloc_list);
alloc_list = g_ptr_array_new();
var = aml_alloc();
return var;
}
void free_aml_allocator(void)
{
g_ptr_array_foreach(alloc_list, aml_free, NULL);
g_ptr_array_free(alloc_list, true);
alloc_list = 0;
}
/* pack data with DefBuffer encoding */
static void build_buffer(GArray *array, uint8_t op)
{
GArray *data = build_alloc_array();
build_append_int(data, array->len);
g_array_prepend_vals(array, data->data, data->len);
build_free_array(data);
build_package(array, op);
}
void aml_append(Aml *parent_ctx, Aml *child)
{
switch (child->block_flags) {
case AML_OPCODE:
build_append_byte(parent_ctx->buf, child->op);
break;
case AML_EXT_PACKAGE:
build_extop_package(child->buf, child->op);
break;
case AML_PACKAGE:
build_package(child->buf, child->op);
break;
case AML_RES_TEMPLATE:
build_append_byte(child->buf, 0x79); /* EndTag */
/*
* checksum operations are treated as succeeded if checksum
* field is zero. [ACPI Spec 1.0b, 6.4.2.8 End Tag]
*/
build_append_byte(child->buf, 0);
/* fall through, to pack resources in buffer */
case AML_BUFFER:
build_buffer(child->buf, child->op);
break;
case AML_NO_OPCODE:
break;
default:
assert(0);
break;
}
build_append_array(parent_ctx->buf, child->buf);
}
/* ACPI 1.0b: 16.2.5.1 Namespace Modifier Objects Encoding: DefScope */
Aml *aml_scope(const char *name_format, ...)
{
va_list ap;
Aml *var = aml_bundle(0x10 /* ScopeOp */, AML_PACKAGE);
va_start(ap, name_format);
build_append_namestringv(var->buf, name_format, ap);
va_end(ap);
return var;
}
/* ACPI 1.0b: 16.2.5.3 Type 1 Opcodes Encoding: DefReturn */
Aml *aml_return(Aml *val)
{
Aml *var = aml_opcode(0xA4 /* ReturnOp */);
aml_append(var, val);
return var;
}
/*
* ACPI 1.0b: 16.2.3 Data Objects Encoding:
* encodes: ByteConst, WordConst, DWordConst, QWordConst, ZeroOp, OneOp
*/
Aml *aml_int(const uint64_t val)
{
Aml *var = aml_alloc();
build_append_int(var->buf, val);
return var;
}
/*
* helper to construct NameString, which returns Aml object
* for using with aml_append or other aml_* terms
*/
Aml *aml_name(const char *name_format, ...)
{
va_list ap;
Aml *var = aml_alloc();
va_start(ap, name_format);
build_append_namestringv(var->buf, name_format, ap);
va_end(ap);
return var;
}
/* ACPI 1.0b: 16.2.5.1 Namespace Modifier Objects Encoding: DefName */
Aml *aml_name_decl(const char *name, Aml *val)
{
Aml *var = aml_opcode(0x08 /* NameOp */);
build_append_namestring(var->buf, "%s", name);
aml_append(var, val);
return var;
}
/* ACPI 1.0b: 16.2.6.1 Arg Objects Encoding */
Aml *aml_arg(int pos)
{
Aml *var;
uint8_t op = 0x68 /* ARG0 op */ + pos;
assert(pos <= 6);
var = aml_opcode(op);
return var;
}
/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefStore */
Aml *aml_store(Aml *val, Aml *target)
{
Aml *var = aml_opcode(0x70 /* StoreOp */);
aml_append(var, val);
aml_append(var, target);
return var;
}
/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefAnd */
Aml *aml_and(Aml *arg1, Aml *arg2)
{
Aml *var = aml_opcode(0x7B /* AndOp */);
aml_append(var, arg1);
aml_append(var, arg2);
build_append_int(var->buf, 0x00 /* NullNameOp */);
return var;
}
/* ACPI 1.0b: 16.2.5.3 Type 1 Opcodes Encoding: DefNotify */
Aml *aml_notify(Aml *arg1, Aml *arg2)
{
Aml *var = aml_opcode(0x86 /* NotifyOp */);
aml_append(var, arg1);
aml_append(var, arg2);
return var;
}
/* helper to call method with 1 argument */
Aml *aml_call1(const char *method, Aml *arg1)
{
Aml *var = aml_alloc();
build_append_namestring(var->buf, "%s", method);
aml_append(var, arg1);
return var;
}
/* helper to call method with 2 arguments */
Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2)
{
Aml *var = aml_alloc();
build_append_namestring(var->buf, "%s", method);
aml_append(var, arg1);
aml_append(var, arg2);
return var;
}
/* helper to call method with 3 arguments */
Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3)
{
Aml *var = aml_alloc();
build_append_namestring(var->buf, "%s", method);
aml_append(var, arg1);
aml_append(var, arg2);
aml_append(var, arg3);
return var;
}
/* helper to call method with 4 arguments */
Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4)
{
Aml *var = aml_alloc();
build_append_namestring(var->buf, "%s", method);
aml_append(var, arg1);
aml_append(var, arg2);
aml_append(var, arg3);
aml_append(var, arg4);
return var;
}
/* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */
Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
uint8_t aln, uint8_t len)
{
Aml *var = aml_alloc();
build_append_byte(var->buf, 0x47); /* IO port descriptor */
build_append_byte(var->buf, dec);
build_append_byte(var->buf, min_base & 0xff);
build_append_byte(var->buf, (min_base >> 8) & 0xff);
build_append_byte(var->buf, max_base & 0xff);
build_append_byte(var->buf, (max_base >> 8) & 0xff);
build_append_byte(var->buf, aln);
build_append_byte(var->buf, len);
return var;
}
/*
* ACPI 1.0b: 6.4.2.1.1 ASL Macro for IRQ Descriptor
*
* More verbose description at:
* ACPI 5.0: 19.5.64 IRQNoFlags (Interrupt Resource Descriptor Macro)
* 6.4.2.1 IRQ Descriptor
*/
Aml *aml_irq_no_flags(uint8_t irq)
{
uint16_t irq_mask;
Aml *var = aml_alloc();
assert(irq < 16);
build_append_byte(var->buf, 0x22); /* IRQ descriptor 2 byte form */
irq_mask = 1U << irq;
build_append_byte(var->buf, irq_mask & 0xFF); /* IRQ mask bits[7:0] */
build_append_byte(var->buf, irq_mask >> 8); /* IRQ mask bits[15:8] */
return var;
}
/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLEqual */
Aml *aml_equal(Aml *arg1, Aml *arg2)
{
Aml *var = aml_opcode(0x93 /* LequalOp */);
aml_append(var, arg1);
aml_append(var, arg2);
build_append_int(var->buf, 0x00); /* NullNameOp */
return var;
}
/* ACPI 1.0b: 16.2.5.3 Type 1 Opcodes Encoding: DefIfElse */
Aml *aml_if(Aml *predicate)
{
Aml *var = aml_bundle(0xA0 /* IfOp */, AML_PACKAGE);
aml_append(var, predicate);
return var;
}
/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefMethod */
Aml *aml_method(const char *name, int arg_count)
{
Aml *var = aml_bundle(0x14 /* MethodOp */, AML_PACKAGE);
build_append_namestring(var->buf, "%s", name);
build_append_byte(var->buf, arg_count); /* MethodFlags: ArgCount */
return var;
}
/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefDevice */
Aml *aml_device(const char *name_format, ...)
{
va_list ap;
Aml *var = aml_bundle(0x82 /* DeviceOp */, AML_EXT_PACKAGE);
va_start(ap, name_format);
build_append_namestringv(var->buf, name_format, ap);
va_end(ap);
return var;
}
/* ACPI 1.0b: 6.4.1 ASL Macros for Resource Descriptors */
Aml *aml_resource_template(void)
{
/* ResourceTemplate is a buffer of Resources with EndTag at the end */
Aml *var = aml_bundle(0x11 /* BufferOp */, AML_RES_TEMPLATE);
return var;
}
/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefBuffer */
Aml *aml_buffer(void)
{
Aml *var = aml_bundle(0x11 /* BufferOp */, AML_BUFFER);
return var;
}
/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefPackage */
Aml *aml_package(uint8_t num_elements)
{
Aml *var = aml_bundle(0x12 /* PackageOp */, AML_PACKAGE);
build_append_byte(var->buf, num_elements);
return var;
}
/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefOpRegion */
Aml *aml_operation_region(const char *name, AmlRegionSpace rs,
uint32_t offset, uint32_t len)
{
Aml *var = aml_alloc();
build_append_byte(var->buf, 0x5B); /* ExtOpPrefix */
build_append_byte(var->buf, 0x80); /* OpRegionOp */
build_append_namestring(var->buf, "%s", name);
build_append_byte(var->buf, rs);
build_append_int(var->buf, offset);
build_append_int(var->buf, len);
return var;
}
/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: NamedField */
Aml *aml_named_field(const char *name, unsigned length)
{
Aml *var = aml_alloc();
build_append_nameseg(var->buf, name);
build_append_pkg_length(var->buf, length, false);
return var;
}
/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: ReservedField */
Aml *aml_reserved_field(unsigned length)
{
Aml *var = aml_alloc();
/* ReservedField := 0x00 PkgLength */
build_append_byte(var->buf, 0x00);
build_append_pkg_length(var->buf, length, false);
return var;
}
/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefField */
Aml *aml_field(const char *name, AmlFieldFlags flags)
{
Aml *var = aml_bundle(0x81 /* FieldOp */, AML_EXT_PACKAGE);
build_append_namestring(var->buf, "%s", name);
build_append_byte(var->buf, flags);
return var;
}
/* ACPI 1.0b: 16.2.3 Data Objects Encoding: String */
Aml *aml_string(const char *name_format, ...)
{
Aml *var = aml_opcode(0x0D /* StringPrefix */);
va_list ap, va_len;
char *s;
int len;
va_start(ap, name_format);
va_copy(va_len, ap);
len = vsnprintf(NULL, 0, name_format, va_len);
va_end(va_len);
len += 1;
s = g_new0(typeof(*s), len);
len = vsnprintf(s, len, name_format, ap);
va_end(ap);
g_array_append_vals(var->buf, s, len);
build_append_byte(var->buf, 0x0); /* NullChar */
g_free(s);
return var;
}
/* ACPI 1.0b: 16.2.6.2 Local Objects Encoding */
Aml *aml_local(int num)
{
Aml *var;
uint8_t op = 0x60 /* Local0Op */ + num;
assert(num <= 7);
var = aml_opcode(op);
return var;
}
/* ACPI 2.0a: 17.2.2 Data Objects Encoding: DefVarPackage */
Aml *aml_varpackage(uint32_t num_elements)
{
Aml *var = aml_bundle(0x13 /* VarPackageOp */, AML_PACKAGE);
build_append_int(var->buf, num_elements);
return var;
}
/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefProcessor */
Aml *aml_processor(uint8_t proc_id, uint32_t pblk_addr, uint8_t pblk_len,
const char *name_format, ...)
{
va_list ap;
Aml *var = aml_bundle(0x83 /* ProcessorOp */, AML_EXT_PACKAGE);
va_start(ap, name_format);
build_append_namestringv(var->buf, name_format, ap);
va_end(ap);
build_append_byte(var->buf, proc_id); /* ProcID */
build_append_int_noprefix(var->buf, pblk_addr, sizeof(pblk_addr));
build_append_byte(var->buf, pblk_len); /* PblkLen */
return var;
}
static uint8_t Hex2Digit(char c)
{
if (c >= 'A') {
return c - 'A' + 10;
}
return c - '0';
}
/* ACPI 1.0b: 15.2.3.6.4.1 EISAID Macro - Convert EISA ID String To Integer */
Aml *aml_eisaid(const char *str)
{
Aml *var = aml_alloc();
uint32_t id;
g_assert(strlen(str) == 7);
id = (str[0] - 0x40) << 26 |
(str[1] - 0x40) << 21 |
(str[2] - 0x40) << 16 |
Hex2Digit(str[3]) << 12 |
Hex2Digit(str[4]) << 8 |
Hex2Digit(str[5]) << 4 |
Hex2Digit(str[6]);
build_append_byte(var->buf, 0x0C); /* DWordPrefix */
build_append_int_noprefix(var->buf, bswap32(id), sizeof(id));
return var;
}
/* ACPI 1.0b: 6.4.3.5.5 Word Address Space Descriptor: bytes 3-5 */
static Aml *aml_as_desc_header(AmlResourceType type, AmlMinFixed min_fixed,
AmlMaxFixed max_fixed, AmlDecode dec,
uint8_t type_flags)
{
uint8_t flags = max_fixed | min_fixed | dec;
Aml *var = aml_alloc();
build_append_byte(var->buf, type);
build_append_byte(var->buf, flags);
build_append_byte(var->buf, type_flags); /* Type Specific Flags */
return var;
}
/* ACPI 1.0b: 6.4.3.5.5 Word Address Space Descriptor */
static Aml *aml_word_as_desc(AmlResourceType type, AmlMinFixed min_fixed,
AmlMaxFixed max_fixed, AmlDecode dec,
uint16_t addr_gran, uint16_t addr_min,
uint16_t addr_max, uint16_t addr_trans,
uint16_t len, uint8_t type_flags)
{
Aml *var = aml_alloc();
build_append_byte(var->buf, 0x88); /* Word Address Space Descriptor */
/* minimum length since we do not encode optional fields */
build_append_byte(var->buf, 0x0D);
build_append_byte(var->buf, 0x0);
aml_append(var,
aml_as_desc_header(type, min_fixed, max_fixed, dec, type_flags));
build_append_int_noprefix(var->buf, addr_gran, sizeof(addr_gran));
build_append_int_noprefix(var->buf, addr_min, sizeof(addr_min));
build_append_int_noprefix(var->buf, addr_max, sizeof(addr_max));
build_append_int_noprefix(var->buf, addr_trans, sizeof(addr_trans));
build_append_int_noprefix(var->buf, len, sizeof(len));
return var;
}
/* ACPI 1.0b: 6.4.3.5.3 DWord Address Space Descriptor */
static Aml *aml_dword_as_desc(AmlResourceType type, AmlMinFixed min_fixed,
AmlMaxFixed max_fixed, AmlDecode dec,
uint32_t addr_gran, uint32_t addr_min,
uint32_t addr_max, uint32_t addr_trans,
uint32_t len, uint8_t type_flags)
{
Aml *var = aml_alloc();
build_append_byte(var->buf, 0x87); /* DWord Address Space Descriptor */
/* minimum length since we do not encode optional fields */
build_append_byte(var->buf, 23);
build_append_byte(var->buf, 0x0);
aml_append(var,
aml_as_desc_header(type, min_fixed, max_fixed, dec, type_flags));
build_append_int_noprefix(var->buf, addr_gran, sizeof(addr_gran));
build_append_int_noprefix(var->buf, addr_min, sizeof(addr_min));
build_append_int_noprefix(var->buf, addr_max, sizeof(addr_max));
build_append_int_noprefix(var->buf, addr_trans, sizeof(addr_trans));
build_append_int_noprefix(var->buf, len, sizeof(len));
return var;
}
/* ACPI 1.0b: 6.4.3.5.1 QWord Address Space Descriptor */
static Aml *aml_qword_as_desc(AmlResourceType type, AmlMinFixed min_fixed,
AmlMaxFixed max_fixed, AmlDecode dec,
uint64_t addr_gran, uint64_t addr_min,
uint64_t addr_max, uint64_t addr_trans,
uint64_t len, uint8_t type_flags)
{
Aml *var = aml_alloc();
build_append_byte(var->buf, 0x8A); /* QWord Address Space Descriptor */
/* minimum length since we do not encode optional fields */
build_append_byte(var->buf, 0x2B);
build_append_byte(var->buf, 0x0);
aml_append(var,
aml_as_desc_header(type, min_fixed, max_fixed, dec, type_flags));
build_append_int_noprefix(var->buf, addr_gran, sizeof(addr_gran));
build_append_int_noprefix(var->buf, addr_min, sizeof(addr_min));
build_append_int_noprefix(var->buf, addr_max, sizeof(addr_max));
build_append_int_noprefix(var->buf, addr_trans, sizeof(addr_trans));
build_append_int_noprefix(var->buf, len, sizeof(len));
return var;
}
/*
* ACPI 1.0b: 6.4.3.5.6 ASL Macros for WORD Address Descriptor
*
* More verbose description at:
* ACPI 5.0: 19.5.141 WordBusNumber (Word Bus Number Resource Descriptor Macro)
*/
Aml *aml_word_bus_number(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
AmlDecode dec, uint16_t addr_gran,
uint16_t addr_min, uint16_t addr_max,
uint16_t addr_trans, uint16_t len)
{
return aml_word_as_desc(aml_bus_number_range, min_fixed, max_fixed, dec,
addr_gran, addr_min, addr_max, addr_trans, len, 0);
}
/*
* ACPI 1.0b: 6.4.3.5.6 ASL Macros for WORD Address Descriptor
*
* More verbose description at:
* ACPI 5.0: 19.5.142 WordIO (Word IO Resource Descriptor Macro)
*/
Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
AmlDecode dec, AmlISARanges isa_ranges,
uint16_t addr_gran, uint16_t addr_min,
uint16_t addr_max, uint16_t addr_trans,
uint16_t len)
{
return aml_word_as_desc(aml_io_range, min_fixed, max_fixed, dec,
addr_gran, addr_min, addr_max, addr_trans, len,
isa_ranges);
}
/*
* ACPI 1.0b: 6.4.3.5.4 ASL Macros for DWORD Address Space Descriptor
*
* More verbose description at:
* ACPI 5.0: 19.5.34 DWordMemory (DWord Memory Resource Descriptor Macro)
*/
Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed,
AmlMaxFixed max_fixed, AmlCacheble cacheable,
AmlReadAndWrite read_and_write,
uint32_t addr_gran, uint32_t addr_min,
uint32_t addr_max, uint32_t addr_trans,
uint32_t len)
{
uint8_t flags = read_and_write | (cacheable << 1);
return aml_dword_as_desc(aml_memory_range, min_fixed, max_fixed,
dec, addr_gran, addr_min, addr_max,
addr_trans, len, flags);
}
/*
* ACPI 1.0b: 6.4.3.5.2 ASL Macros for QWORD Address Space Descriptor
*
* More verbose description at:
* ACPI 5.0: 19.5.102 QWordMemory (QWord Memory Resource Descriptor Macro)
*/
Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
AmlMaxFixed max_fixed, AmlCacheble cacheable,
AmlReadAndWrite read_and_write,
uint64_t addr_gran, uint64_t addr_min,
uint64_t addr_max, uint64_t addr_trans,
uint64_t len)
{
uint8_t flags = read_and_write | (cacheable << 1);
return aml_qword_as_desc(aml_memory_range, min_fixed, max_fixed,
dec, addr_gran, addr_min, addr_max,
addr_trans, len, flags);
}

4
hw/acpi/bios-linker-loader.c
View File

@ -141,6 +141,7 @@ void bios_linker_loader_add_pointer(GArray *linker,
uint8_t pointer_size)
{
BiosLinkerLoaderEntry entry;
size_t offset = (gchar *)pointer - table->data;
memset(&entry, 0, sizeof entry);
strncpy(entry.pointer.dest_file, dest_file,
@ -148,7 +149,8 @@ void bios_linker_loader_add_pointer(GArray *linker,
strncpy(entry.pointer.src_file, src_file,
sizeof entry.pointer.src_file - 1);
entry.command = cpu_to_le32(BIOS_LINKER_LOADER_COMMAND_ADD_POINTER);
entry.pointer.offset = cpu_to_le32((gchar *)pointer - table->data);
assert(table->len >= offset + pointer_size);
entry.pointer.offset = cpu_to_le32(offset);
entry.pointer.size = pointer_size;
assert(pointer_size == 1 || pointer_size == 2 ||
pointer_size == 4 || pointer_size == 8);

14
hw/acpi/ich9.c
View File

@ -397,6 +397,20 @@ void ich9_pm_device_plug_cb(ICH9LPCPMRegs *pm, DeviceState *dev, Error **errp)
}
}
void ich9_pm_device_unplug_request_cb(ICH9LPCPMRegs *pm, DeviceState *dev,
Error **errp)
{
error_setg(errp, "acpi: device unplug request for not supported device"
" type: %s", object_get_typename(OBJECT(dev)));
}
void ich9_pm_device_unplug_cb(ICH9LPCPMRegs *pm, DeviceState *dev,
Error **errp)
{
error_setg(errp, "acpi: device unplug for not supported device"
" type: %s", object_get_typename(OBJECT(dev)));
}
void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
{
ICH9LPCState *s = ICH9_LPC_DEVICE(adev);

3
hw/acpi/memory_hotplug.c
View File

@ -168,7 +168,8 @@ void acpi_memory_plug_cb(ACPIREGS *ar, qemu_irq irq, MemHotplugState *mem_st,
{
MemStatus *mdev;
Error *local_err = NULL;
int slot = object_property_get_int(OBJECT(dev), "slot", &local_err);
int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
&local_err);
if (local_err) {
error_propagate(errp, local_err);

18
hw/acpi/pcihp.c
View File

@ -297,10 +297,11 @@ static const MemoryRegionOps acpi_pcihp_io_ops = {
},
};
void acpi_pcihp_init(AcpiPciHpState *s, PCIBus *root_bus,
void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
MemoryRegion *address_space_io, bool bridges_enabled)
{
uint16_t io_size = ACPI_PCIHP_SIZE;
s->io_len = ACPI_PCIHP_SIZE;
s->io_base = ACPI_PCIHP_ADDR;
s->root= root_bus;
s->legacy_piix = !bridges_enabled;
@ -308,16 +309,21 @@ void acpi_pcihp_init(AcpiPciHpState *s, PCIBus *root_bus,
if (s->legacy_piix) {
unsigned *bus_bsel = g_malloc(sizeof *bus_bsel);
io_size = ACPI_PCIHP_LEGACY_SIZE;
s->io_len = ACPI_PCIHP_LEGACY_SIZE;
*bus_bsel = ACPI_PCIHP_BSEL_DEFAULT;
object_property_add_uint32_ptr(OBJECT(root_bus), ACPI_PCIHP_PROP_BSEL,
bus_bsel, NULL);
}
memory_region_init_io(&s->io, NULL, &acpi_pcihp_io_ops, s,
"acpi-pci-hotplug", io_size);
memory_region_add_subregion(address_space_io, ACPI_PCIHP_ADDR, &s->io);
memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s,
"acpi-pci-hotplug", s->io_len);
memory_region_add_subregion(address_space_io, s->io_base, &s->io);
object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_BASE_PROP, &s->io_base,
&error_abort);
object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_LEN_PROP, &s->io_len,
&error_abort);
}
const VMStateDescription vmstate_acpi_pcihp_pci_status = {

15
hw/acpi/piix4.c
View File

@ -370,6 +370,13 @@ static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
}
}
static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
error_setg(errp, "acpi: device unplug for not supported device"
" type: %s", object_get_typename(OBJECT(dev)));
}
static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque)
{
PIIX4PMState *s = opaque;
@ -420,7 +427,7 @@ static void piix4_pm_add_propeties(PIIX4PMState *s)
&s->io_base, NULL);
}
static int piix4_pm_initfn(PCIDevice *dev)
static void piix4_pm_realize(PCIDevice *dev, Error **errp)
{
PIIX4PMState *s = PIIX4_PM(dev);
uint8_t *pci_conf;
@ -470,7 +477,6 @@ static int piix4_pm_initfn(PCIDevice *dev)
piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s);
piix4_pm_add_propeties(s);
return 0;
}
Object *piix4_pm_find(void)
@ -556,7 +562,7 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
"acpi-gpe0", GPE_LEN);
memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent,
acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
s->use_acpi_pci_hotplug);
acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
@ -593,7 +599,7 @@ static void piix4_pm_class_init(ObjectClass *klass, void *data)
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
k->init = piix4_pm_initfn;
k->realize = piix4_pm_realize;
k->config_write = pm_write_config;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
@ -610,6 +616,7 @@ static void piix4_pm_class_init(ObjectClass *klass, void *data)
dc->hotpluggable = false;
hc->plug = piix4_device_plug_cb;
hc->unplug_request = piix4_device_unplug_request_cb;
hc->unplug = piix4_device_unplug_cb;
adevc->ospm_status = piix4_ospm_status;
}

5
hw/audio/ac97.c
View File

@ -1337,7 +1337,7 @@ static void ac97_on_reset (DeviceState *dev)
mixer_reset (s);
}
static int ac97_initfn (PCIDevice *dev)
static void ac97_realize(PCIDevice *dev, Error **errp)
{
AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
uint8_t *c = s->dev.config;
@ -1384,7 +1384,6 @@ static int ac97_initfn (PCIDevice *dev)
pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
AUD_register_card ("ac97", &s->card);
ac97_on_reset (&s->dev.qdev);
return 0;
}
static int ac97_init (PCIBus *bus)
@ -1403,7 +1402,7 @@ static void ac97_class_init (ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS (klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS (klass);
k->init = ac97_initfn;
k->realize = ac97_realize;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82801AA_5;
k->revision = 0x01;

5
hw/audio/es1370.c
View File

@ -1016,7 +1016,7 @@ static void es1370_on_reset (void *opaque)
es1370_reset (s);
}
static int es1370_initfn (PCIDevice *dev)
static void es1370_realize(PCIDevice *dev, Error **errp)
{
ES1370State *s = DO_UPCAST (ES1370State, dev, dev);
uint8_t *c = s->dev.config;
@ -1039,7 +1039,6 @@ static int es1370_initfn (PCIDevice *dev)
AUD_register_card ("es1370", &s->card);
es1370_reset (s);
return 0;
}
static int es1370_init (PCIBus *bus)
@ -1053,7 +1052,7 @@ static void es1370_class_init (ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS (klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS (klass);
k->init = es1370_initfn;
k->realize = es1370_realize;
k->vendor_id = PCI_VENDOR_ID_ENSONIQ;
k->device_id = PCI_DEVICE_ID_ENSONIQ_ES1370;
k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;

6
hw/audio/intel-hda.c
View File

@ -1126,7 +1126,7 @@ static void intel_hda_reset(DeviceState *dev)
intel_hda_update_irq(d);
}
static int intel_hda_init(PCIDevice *pci)
static void intel_hda_realize(PCIDevice *pci, Error **errp)
{
IntelHDAState *d = INTEL_HDA(pci);
uint8_t *conf = d->pci.config;
@ -1147,8 +1147,6 @@ static int intel_hda_init(PCIDevice *pci)
hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs),
intel_hda_response, intel_hda_xfer);
return 0;
}
static void intel_hda_exit(PCIDevice *pci)
@ -1245,7 +1243,7 @@ static void intel_hda_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = intel_hda_init;
k->realize = intel_hda_realize;
k->exit = intel_hda_exit;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;

31
hw/block/virtio-blk.c
View File

@ -667,11 +667,11 @@ static void virtio_blk_update_config(VirtIODevice *vdev, uint8_t *config)
memset(&blkcfg, 0, sizeof(blkcfg));
virtio_stq_p(vdev, &blkcfg.capacity, capacity);
virtio_stl_p(vdev, &blkcfg.seg_max, 128 - 2);
virtio_stw_p(vdev, &blkcfg.cylinders, conf->cyls);
virtio_stw_p(vdev, &blkcfg.geometry.cylinders, conf->cyls);
virtio_stl_p(vdev, &blkcfg.blk_size, blk_size);
virtio_stw_p(vdev, &blkcfg.min_io_size, conf->min_io_size / blk_size);
virtio_stw_p(vdev, &blkcfg.opt_io_size, conf->opt_io_size / blk_size);
blkcfg.heads = conf->heads;
blkcfg.geometry.heads = conf->heads;
/*
* We must ensure that the block device capacity is a multiple of
* the logical block size. If that is not the case, let's use
@ -684,9 +684,9 @@ static void virtio_blk_update_config(VirtIODevice *vdev, uint8_t *config)
* per track (cylinder).
*/
if (blk_getlength(s->blk) / conf->heads / conf->secs % blk_size) {
blkcfg.sectors = conf->secs & ~s->sector_mask;
blkcfg.geometry.sectors = conf->secs & ~s->sector_mask;
} else {
blkcfg.sectors = conf->secs;
blkcfg.geometry.sectors = conf->secs;
}
blkcfg.size_max = 0;
blkcfg.physical_block_exp = get_physical_block_exp(conf);
@ -711,20 +711,20 @@ static uint32_t virtio_blk_get_features(VirtIODevice *vdev, uint32_t features)
{
VirtIOBlock *s = VIRTIO_BLK(vdev);
features |= (1 << VIRTIO_BLK_F_SEG_MAX);
features |= (1 << VIRTIO_BLK_F_GEOMETRY);
features |= (1 << VIRTIO_BLK_F_TOPOLOGY);
features |= (1 << VIRTIO_BLK_F_BLK_SIZE);
features |= (1 << VIRTIO_BLK_F_SCSI);
virtio_add_feature(&features, VIRTIO_BLK_F_SEG_MAX);
virtio_add_feature(&features, VIRTIO_BLK_F_GEOMETRY);
virtio_add_feature(&features, VIRTIO_BLK_F_TOPOLOGY);
virtio_add_feature(&features, VIRTIO_BLK_F_BLK_SIZE);
virtio_add_feature(&features, VIRTIO_BLK_F_SCSI);
if (s->conf.config_wce) {
features |= (1 << VIRTIO_BLK_F_CONFIG_WCE);
virtio_add_feature(&features, VIRTIO_BLK_F_CONFIG_WCE);
}
if (blk_enable_write_cache(s->blk)) {
features |= (1 << VIRTIO_BLK_F_WCE);
virtio_add_feature(&features, VIRTIO_BLK_F_WCE);
}
if (blk_is_read_only(s->blk)) {
features |= 1 << VIRTIO_BLK_F_RO;
virtio_add_feature(&features, VIRTIO_BLK_F_RO);
}
return features;
@ -733,7 +733,6 @@ static uint32_t virtio_blk_get_features(VirtIODevice *vdev, uint32_t features)
static void virtio_blk_set_status(VirtIODevice *vdev, uint8_t status)
{
VirtIOBlock *s = VIRTIO_BLK(vdev);
uint32_t features;
if (s->dataplane && !(status & (VIRTIO_CONFIG_S_DRIVER |
VIRTIO_CONFIG_S_DRIVER_OK))) {
@ -744,8 +743,6 @@ static void virtio_blk_set_status(VirtIODevice *vdev, uint8_t status)
return;
}
features = vdev->guest_features;
/* A guest that supports VIRTIO_BLK_F_CONFIG_WCE must be able to send
* cache flushes. Thus, the "auto writethrough" behavior is never
* necessary for guests that support the VIRTIO_BLK_F_CONFIG_WCE feature.
@ -761,10 +758,10 @@ static void virtio_blk_set_status(VirtIODevice *vdev, uint8_t status)
*
* s->blk would erroneously be placed in writethrough mode.
*/
if (!(features & (1 << VIRTIO_BLK_F_CONFIG_WCE))) {
if (!virtio_has_feature(vdev, VIRTIO_BLK_F_CONFIG_WCE)) {
aio_context_acquire(blk_get_aio_context(s->blk));
blk_set_enable_write_cache(s->blk,
!!(features & (1 << VIRTIO_BLK_F_WCE)));
virtio_has_feature(vdev, VIRTIO_BLK_F_WCE));
aio_context_release(blk_get_aio_context(s->blk));
}
}

22
hw/char/serial-pci.c
View File

@ -48,7 +48,7 @@ typedef struct PCIMultiSerialState {
uint8_t prog_if;
} PCIMultiSerialState;
static int serial_pci_init(PCIDevice *dev)
static void serial_pci_realize(PCIDevice *dev, Error **errp)
{
PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
SerialState *s = &pci->state;
@ -57,9 +57,8 @@ static int serial_pci_init(PCIDevice *dev)
s->baudbase = 115200;
serial_realize_core(s, &err);
if (err != NULL) {
qerror_report_err(err);
error_free(err);
return -1;
error_propagate(errp, err);
return;
}
pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
@ -68,7 +67,6 @@ static int serial_pci_init(PCIDevice *dev)
memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, "serial", 8);
pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
return 0;
}
static void multi_serial_irq_mux(void *opaque, int n, int level)
@ -85,7 +83,7 @@ static void multi_serial_irq_mux(void *opaque, int n, int level)
pci_set_irq(&pci->dev, pending);
}
static int multi_serial_pci_init(PCIDevice *dev)
static void multi_serial_pci_realize(PCIDevice *dev, Error **errp)
{
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
@ -116,9 +114,8 @@ static int multi_serial_pci_init(PCIDevice *dev)
s->baudbase = 115200;
serial_realize_core(s, &err);
if (err != NULL) {
qerror_report_err(err);
error_free(err);
return -1;
error_propagate(errp, err);
return;
}
s->irq = pci->irqs[i];
pci->name[i] = g_strdup_printf("uart #%d", i+1);
@ -126,7 +123,6 @@ static int multi_serial_pci_init(PCIDevice *dev)
pci->name[i], 8);
memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
}
return 0;
}
static void serial_pci_exit(PCIDevice *dev)
@ -203,7 +199,7 @@ static void serial_pci_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
pc->init = serial_pci_init;
pc->realize = serial_pci_realize;
pc->exit = serial_pci_exit;
pc->vendor_id = PCI_VENDOR_ID_REDHAT;
pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL;
@ -218,7 +214,7 @@ static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
pc->init = multi_serial_pci_init;
pc->realize = multi_serial_pci_realize;
pc->exit = multi_serial_pci_exit;
pc->vendor_id = PCI_VENDOR_ID_REDHAT;
pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
@ -233,7 +229,7 @@ static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
pc->init = multi_serial_pci_init;
pc->realize = multi_serial_pci_realize;
pc->exit = multi_serial_pci_exit;
pc->vendor_id = PCI_VENDOR_ID_REDHAT;
pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;

4
hw/char/virtio-serial-bus.c
View File

@ -75,7 +75,7 @@ static VirtIOSerialPort *find_port_by_name(char *name)
static bool use_multiport(VirtIOSerial *vser)
{
VirtIODevice *vdev = VIRTIO_DEVICE(vser);
return vdev->guest_features & (1 << VIRTIO_CONSOLE_F_MULTIPORT);
return virtio_has_feature(vdev, VIRTIO_CONSOLE_F_MULTIPORT);
}
static size_t write_to_port(VirtIOSerialPort *port,
@ -474,7 +474,7 @@ static uint32_t get_features(VirtIODevice *vdev, uint32_t features)
vser = VIRTIO_SERIAL(vdev);
if (vser->bus.max_nr_ports > 1) {
features |= (1 << VIRTIO_CONSOLE_F_MULTIPORT);
virtio_add_feature(&features, VIRTIO_CONSOLE_F_MULTIPORT);
}
return features;
}

21
hw/core/qdev-properties.c
View File

@ -990,8 +990,8 @@ int qdev_prop_check_globals(void)
return ret;
}
void qdev_prop_set_globals_for_type(DeviceState *dev, const char *typename,
Error **errp)
static void qdev_prop_set_globals_for_type(DeviceState *dev,
const char *typename)
{
GlobalProperty *prop;
@ -1004,25 +1004,22 @@ void qdev_prop_set_globals_for_type(DeviceState *dev, const char *typename,
prop->used = true;
object_property_parse(OBJECT(dev), prop->value, prop->property, &err);
if (err != NULL) {
error_propagate(errp, err);
assert(prop->user_provided);
error_report("Warning: global %s.%s=%s ignored (%s)",
prop->driver, prop->property, prop->value,
error_get_pretty(err));
error_free(err);
return;
}
}
}
void qdev_prop_set_globals(DeviceState *dev, Error **errp)
void qdev_prop_set_globals(DeviceState *dev)
{
ObjectClass *class = object_get_class(OBJECT(dev));
do {
Error *err = NULL;
qdev_prop_set_globals_for_type(dev, object_class_get_name(class),
&err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
qdev_prop_set_globals_for_type(dev, object_class_get_name(class));
class = object_class_get_parent(class);
} while (class);
}

8
hw/core/qdev.c
View File

@ -1196,13 +1196,7 @@ static void device_initfn(Object *obj)
static void device_post_init(Object *obj)
{
Error *err = NULL;
qdev_prop_set_globals(DEVICE(obj), &err);
if (err) {
qerror_report_err(err);
error_free(err);
exit(EXIT_FAILURE);
}
qdev_prop_set_globals(DEVICE(obj));
}
/* Unlink device from bus and free the structure. */

11
hw/display/cirrus_vga.c
View File

@ -3006,7 +3006,7 @@ static const TypeInfo isa_cirrus_vga_info = {
*
***************************************/
static int pci_cirrus_vga_initfn(PCIDevice *dev)
static void pci_cirrus_vga_realize(PCIDevice *dev, Error **errp)
{
PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
CirrusVGAState *s = &d->cirrus_vga;
@ -3017,9 +3017,9 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
Also accept 8 MB/16 MB for backward compatibility. */
if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 &&
s->vga.vram_size_mb != 16) {
error_report("Invalid cirrus_vga ram size '%u'",
s->vga.vram_size_mb);
return -1;
error_setg(errp, "Invalid cirrus_vga ram size '%u'",
s->vga.vram_size_mb);
return;
}
/* setup VGA */
vga_common_init(&s->vga, OBJECT(dev), true);
@ -3044,7 +3044,6 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
if (device_id == CIRRUS_ID_CLGD5446) {
pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
}
return 0;
}
static Property pci_vga_cirrus_properties[] = {
@ -3058,7 +3057,7 @@ static void cirrus_vga_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_cirrus_vga_initfn;
k->realize = pci_cirrus_vga_realize;
k->romfile = VGABIOS_CIRRUS_FILENAME;
k->vendor_id = PCI_VENDOR_ID_CIRRUS;
k->device_id = CIRRUS_ID_CLGD5446;

36
hw/display/qxl.c
View File

@ -1913,7 +1913,7 @@ static void qxl_init_ramsize(PCIQXLDevice *qxl)
qxl->vram_size = pow2ceil(qxl->vram_size);
}
static int qxl_init_common(PCIQXLDevice *qxl)
static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
{
uint8_t* config = qxl->pci.config;
uint32_t pci_device_rev;
@ -1945,9 +1945,9 @@ static int qxl_init_common(PCIQXLDevice *qxl)
io_size = pow2ceil(QXL_IO_RANGE_SIZE);
break;
default:
error_report("Invalid revision %d for qxl device (max %d)",
qxl->revision, QXL_DEFAULT_REVISION);
return -1;
error_setg(errp, "Invalid revision %d for qxl device (max %d)",
qxl->revision, QXL_DEFAULT_REVISION);
return;
}
pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
@ -2011,9 +2011,9 @@ static int qxl_init_common(PCIQXLDevice *qxl)
qxl->ssd.qxl.base.sif = &qxl_interface.base;
if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
error_report("qxl interface %d.%d not supported by spice-server",
SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
return -1;
error_setg(errp, "qxl interface %d.%d not supported by spice-server",
SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
return;
}
qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
@ -2022,15 +2022,13 @@ static int qxl_init_common(PCIQXLDevice *qxl)
qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
return 0;
}
static int qxl_init_primary(PCIDevice *dev)
static void qxl_realize_primary(PCIDevice *dev, Error **errp)
{
PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
VGACommonState *vga = &qxl->vga;
int rc;
Error *local_err = NULL;
qxl->id = 0;
qxl_init_ramsize(qxl);
@ -2047,18 +2045,18 @@ static int qxl_init_primary(PCIDevice *dev)
vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
qemu_spice_display_init_common(&qxl->ssd);
rc = qxl_init_common(qxl);
if (rc != 0) {
return rc;
qxl_realize_common(qxl, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
qxl->ssd.dcl.ops = &display_listener_ops;
qxl->ssd.dcl.con = vga->con;
register_displaychangelistener(&qxl->ssd.dcl);
return rc;
}
static int qxl_init_secondary(PCIDevice *dev)
static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
{
static int device_id = 1;
PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
@ -2071,7 +2069,7 @@ static int qxl_init_secondary(PCIDevice *dev)
qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
return qxl_init_common(qxl);
qxl_realize_common(qxl, errp);
}
static void qxl_pre_save(void *opaque)
@ -2284,7 +2282,7 @@ static void qxl_primary_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = qxl_init_primary;
k->realize = qxl_realize_primary;
k->romfile = "vgabios-qxl.bin";
k->vendor_id = REDHAT_PCI_VENDOR_ID;
k->device_id = QXL_DEVICE_ID_STABLE;
@ -2309,7 +2307,7 @@ static void qxl_secondary_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = qxl_init_secondary;
k->realize = qxl_realize_secondary;
k->vendor_id = REDHAT_PCI_VENDOR_ID;
k->device_id = QXL_DEVICE_ID_STABLE;
k->class_id = PCI_CLASS_DISPLAY_OTHER;

11
hw/display/vga-pci.c
View File

@ -189,7 +189,7 @@ static const MemoryRegionOps pci_vga_qext_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static int pci_std_vga_initfn(PCIDevice *dev)
static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
{
PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
VGACommonState *s = &d->vga;
@ -232,11 +232,9 @@ static int pci_std_vga_initfn(PCIDevice *dev)
/* compatibility with pc-0.13 and older */
vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
}
return 0;
}
static int pci_secondary_vga_initfn(PCIDevice *dev)
static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
{
PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
VGACommonState *s = &d->vga;
@ -268,7 +266,6 @@ static int pci_secondary_vga_initfn(PCIDevice *dev)
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
return 0;
}
static void pci_secondary_vga_reset(DeviceState *dev)
@ -298,7 +295,7 @@ static void vga_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_std_vga_initfn;
k->realize = pci_std_vga_realize;
k->romfile = "vgabios-stdvga.bin";
k->vendor_id = PCI_VENDOR_ID_QEMU;
k->device_id = PCI_DEVICE_ID_QEMU_VGA;
@ -314,7 +311,7 @@ static void secondary_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_secondary_vga_initfn;
k->realize = pci_secondary_vga_realize;
k->vendor_id = PCI_VENDOR_ID_QEMU;
k->device_id = PCI_DEVICE_ID_QEMU_VGA;
k->class_id = PCI_CLASS_DISPLAY_OTHER;

6
hw/display/vmware_vga.c
View File

@ -1298,7 +1298,7 @@ static const MemoryRegionOps vmsvga_io_ops = {
},
};
static int pci_vmsvga_initfn(PCIDevice *dev)
static void pci_vmsvga_realize(PCIDevice *dev, Error **errp)
{
struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev);
@ -1323,8 +1323,6 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
/* compatibility with pc-0.13 and older */
vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev));
}
return 0;
}
static Property vga_vmware_properties[] = {
@ -1338,7 +1336,7 @@ static void vmsvga_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_vmsvga_initfn;
k->realize = pci_vmsvga_realize;
k->romfile = "vgabios-vmware.bin";
k->vendor_id = PCI_VENDOR_ID_VMWARE;
k->device_id = SVGA_PCI_DEVICE_ID;

5
hw/i2c/smbus_ich9.c
View File

@ -71,7 +71,7 @@ static void ich9_smbus_write_config(PCIDevice *d, uint32_t address,
}
}
static int ich9_smbus_initfn(PCIDevice *d)
static void ich9_smbus_realize(PCIDevice *d, Error **errp)
{
ICH9SMBState *s = ICH9_SMB_DEVICE(d);
@ -84,7 +84,6 @@ static int ich9_smbus_initfn(PCIDevice *d)
pm_smbus_init(&d->qdev, &s->smb);
pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
&s->smb.io);
return 0;
}
static void ich9_smb_class_init(ObjectClass *klass, void *data)
@ -98,7 +97,7 @@ static void ich9_smb_class_init(ObjectClass *klass, void *data)
k->class_id = PCI_CLASS_SERIAL_SMBUS;
dc->vmsd = &vmstate_ich9_smbus;
dc->desc = "ICH9 SMBUS Bridge";
k->init = ich9_smbus_initfn;
k->realize = ich9_smbus_realize;
k->config_write = ich9_smbus_write_config;
/*
* Reason: part of ICH9 southbridge, needs to be wired up by

4
hw/i386/Makefile.objs
View File

@ -7,10 +7,8 @@ obj-$(CONFIG_XEN) += ../xenpv/ xen/
obj-y += kvmvapic.o
obj-y += acpi-build.o
hw/i386/acpi-build.o: hw/i386/acpi-build.c hw/i386/acpi-dsdt.hex \
hw/i386/ssdt-proc.hex hw/i386/ssdt-pcihp.hex hw/i386/ssdt-misc.hex \
hw/i386/acpi-build.o: hw/i386/acpi-build.c \
hw/i386/acpi-dsdt.hex hw/i386/q35-acpi-dsdt.hex \
hw/i386/q35-acpi-dsdt.hex hw/i386/ssdt-mem.hex \
hw/i386/ssdt-tpm.hex
iasl-option=$(shell if test -z "`$(1) $(2) 2>&1 > /dev/null`" \

1185
hw/i386/acpi-build.c
View File

File diff suppressed because it is too large Load Diff

17
hw/i386/acpi-dsdt-cpu-hotplug.dsl
View File

@ -16,12 +16,12 @@
/****************************************************************
* CPU hotplug
****************************************************************/
#define CPU_HOTPLUG_RESOURCE_DEVICE PRES
Scope(\_SB) {
/* Objects filled in by run-time generated SSDT */
External(NTFY, MethodObj)
External(CPON, PkgObj)
External(PRS, FieldUnitObj)
/* Methods called by run-time generated SSDT Processor objects */
Method(CPMA, 1, NotSerialized) {
@ -54,10 +54,6 @@ Scope(\_SB) {
}
#define CPU_STATUS_LEN ACPI_GPE_PROC_LEN
OperationRegion(PRST, SystemIO, CPU_STATUS_BASE, CPU_STATUS_LEN)
Field(PRST, ByteAcc, NoLock, Preserve) {
PRS, 256
}
Method(PRSC, 0) {
// Local5 = active cpu bitmap
Store(PRS, Local5)
@ -91,15 +87,4 @@ Scope(\_SB) {
Increment(Local0)
}
}
Device(CPU_HOTPLUG_RESOURCE_DEVICE) {
Name(_HID, EisaId("PNP0A06"))
Name(_UID, "CPU hotplug resources")
Name(_CRS, ResourceTemplate() {
IO(Decode16, CPU_STATUS_BASE, CPU_STATUS_BASE, 0, CPU_STATUS_LEN)
})
Name(_STA, 0xB) /* present, functioning, decoding, not shown in UI */
}
}

11
hw/i386/acpi-dsdt-isa.dsl
View File

@ -16,17 +16,6 @@
/* Common legacy ISA style devices. */
Scope(\_SB.PCI0.ISA) {
Device (SMC) {
Name(_HID, EisaId("APP0001"))
/* _STA will be patched to 0x0B if AppleSMC is present */
ACPI_EXTRACT_NAME_BYTE_CONST DSDT_APPLESMC_STA
Name(_STA, 0xF0)
Name(_CRS, ResourceTemplate () {
IO (Decode16, 0x0300, 0x0300, 0x01, 0x20)
IRQNoFlags() { 6 }
})
}
Device(RTC) {
Name(_HID, EisaId("PNP0B00"))
Name(_CRS, ResourceTemplate() {

36
hw/i386/acpi-dsdt-mem-hotplug.dsl
View File

@ -22,14 +22,16 @@
External(MEMORY_SLOTS_NUMBER, IntObj)
/* Memory hotplug IO registers */
OperationRegion(MEMORY_HOTPLUG_IO_REGION, SystemIO,
ACPI_MEMORY_HOTPLUG_BASE,
ACPI_MEMORY_HOTPLUG_IO_LEN)
Name(_CRS, ResourceTemplate() {
IO(Decode16, ACPI_MEMORY_HOTPLUG_BASE, ACPI_MEMORY_HOTPLUG_BASE,
0, ACPI_MEMORY_HOTPLUG_IO_LEN, IO)
})
External(MEMORY_SLOT_ADDR_LOW, FieldUnitObj) // read only
External(MEMORY_SLOT_ADDR_HIGH, FieldUnitObj) // read only
External(MEMORY_SLOT_SIZE_LOW, FieldUnitObj) // read only
External(MEMORY_SLOT_SIZE_HIGH, FieldUnitObj) // read only
External(MEMORY_SLOT_PROXIMITY, FieldUnitObj) // read only
External(MEMORY_SLOT_ENABLED, FieldUnitObj) // 1 if enabled, read only
External(MEMORY_SLOT_INSERT_EVENT, FieldUnitObj) // (read) 1 if has a insert event. (write) 1 to clear event
External(MEMORY_SLOT_SLECTOR, FieldUnitObj) // DIMM selector, write only
External(MEMORY_SLOT_OST_EVENT, FieldUnitObj) // _OST event code, write only
External(MEMORY_SLOT_OST_STATUS, FieldUnitObj) // _OST status code, write only
Method(_STA, 0) {
If (LEqual(MEMORY_SLOTS_NUMBER, Zero)) {
@ -39,25 +41,7 @@
Return(0xB)
}
Field(MEMORY_HOTPLUG_IO_REGION, DWordAcc, NoLock, Preserve) {
MEMORY_SLOT_ADDR_LOW, 32, // read only
MEMORY_SLOT_ADDR_HIGH, 32, // read only
MEMORY_SLOT_SIZE_LOW, 32, // read only
MEMORY_SLOT_SIZE_HIGH, 32, // read only
MEMORY_SLOT_PROXIMITY, 32, // read only
}
Field(MEMORY_HOTPLUG_IO_REGION, ByteAcc, NoLock, Preserve) {
Offset(20),
MEMORY_SLOT_ENABLED, 1, // 1 if enabled, read only
MEMORY_SLOT_INSERT_EVENT, 1, // (read) 1 if has a insert event. (write) 1 to clear event
}
Mutex (MEMORY_SLOT_LOCK, 0)
Field (MEMORY_HOTPLUG_IO_REGION, DWordAcc, NoLock, Preserve) {
MEMORY_SLOT_SLECTOR, 32, // DIMM selector, write only
MEMORY_SLOT_OST_EVENT, 32, // _OST event code, write only
MEMORY_SLOT_OST_STATUS, 32, // _OST status code, write only
}
Method(MEMORY_SLOT_SCAN_METHOD, 0) {
If (LEqual(MEMORY_SLOTS_NUMBER, Zero)) {

92
hw/i386/acpi-dsdt-pci-crs.dsl
View File

@ -1,92 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
/* PCI CRS (current resources) definition. */
Scope(\_SB.PCI0) {
Name(CRES, ResourceTemplate() {
WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Address Space Granularity
0x0000, // Address Range Minimum
0x00FF, // Address Range Maximum
0x0000, // Address Translation Offset
0x0100, // Address Length
,, )
IO(Decode16,
0x0CF8, // Address Range Minimum
0x0CF8, // Address Range Maximum
0x01, // Address Alignment
0x08, // Address Length
)
BOARD_SPECIFIC_PCI_RESOURSES
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000, // Address Space Granularity
0x000A0000, // Address Range Minimum
0x000BFFFF, // Address Range Maximum
0x00000000, // Address Translation Offset
0x00020000, // Address Length
,, , AddressRangeMemory, TypeStatic)
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Address Space Granularity
0xE0000000, // Address Range Minimum
0xFEBFFFFF, // Address Range Maximum
0x00000000, // Address Translation Offset
0x1EC00000, // Address Length
,, PW32, AddressRangeMemory, TypeStatic)
})
Name(CR64, ResourceTemplate() {
QWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000, // Address Space Granularity
0x8000000000, // Address Range Minimum
0xFFFFFFFFFF, // Address Range Maximum
0x00000000, // Address Translation Offset
0x8000000000, // Address Length
,, PW64, AddressRangeMemory, TypeStatic)
})
Method(_CRS, 0) {
/* Fields provided by dynamically created ssdt */
External(P0S, IntObj)
External(P0E, IntObj)
External(P1V, IntObj)
External(P1S, BuffObj)
External(P1E, BuffObj)
External(P1L, BuffObj)
/* fixup 32bit pci io window */
CreateDWordField(CRES, \_SB.PCI0.PW32._MIN, PS32)
CreateDWordField(CRES, \_SB.PCI0.PW32._MAX, PE32)
CreateDWordField(CRES, \_SB.PCI0.PW32._LEN, PL32)
Store(P0S, PS32)
Store(P0E, PE32)
Store(Add(Subtract(P0E, P0S), 1), PL32)
If (LEqual(P1V, Zero)) {
Return (CRES)
}
/* fixup 64bit pci io window */
CreateQWordField(CR64, \_SB.PCI0.PW64._MIN, PS64)
CreateQWordField(CR64, \_SB.PCI0.PW64._MAX, PE64)
CreateQWordField(CR64, \_SB.PCI0.PW64._LEN, PL64)
Store(P1S, PS64)
Store(P1E, PE64)
Store(P1L, PL64)
/* add window and return result */
ConcatenateResTemplate(CRES, CR64, Local0)
Return (Local0)
}
}

46
hw/i386/acpi-dsdt.dsl
View File

@ -31,50 +31,6 @@ DefinitionBlock (
#include "acpi-dsdt-dbug.dsl"
/****************************************************************
* PCI Bus definition
****************************************************************/
#define BOARD_SPECIFIC_PCI_RESOURSES \
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
0x0000, \
0x0000, \
0x0CF7, \
0x0000, \
0x0CF8, \
,, , TypeStatic) \
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
0x0000, \
0x0D00, \
0xADFF, \
0x0000, \
0xA100, \
,, , TypeStatic) \
/* 0xae00-0xae0e hole for PCI hotplug, hw/acpi/piix4.c:PCI_HOTPLUG_ADDR */ \
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
0x0000, \
0xAE0F, \
0xAEFF, \
0x0000, \
0x00F1, \
,, , TypeStatic) \
/* 0xaf00-0xaf1f hole for CPU hotplug, hw/acpi/piix4.c:PIIX4_PROC_BASE */ \
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
0x0000, \
0xAF20, \
0xAFDF, \
0x0000, \
0x00C0, \
,, , TypeStatic) \
/* 0xafe0-0xafe3 hole for ACPI.GPE0, hw/acpi/piix4.c:GPE_BASE */ \
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
0x0000, \
0xAFE4, \
0xFFFF, \
0x0000, \
0x501C, \
,, , TypeStatic)
Scope(\_SB) {
Device(PCI0) {
Name(_HID, EisaId("PNP0A03"))
@ -85,7 +41,6 @@ DefinitionBlock (
}
}
#include "acpi-dsdt-pci-crs.dsl"
#include "acpi-dsdt-hpet.dsl"
@ -130,7 +85,6 @@ DefinitionBlock (
}
}
#define DSDT_APPLESMC_STA piix_dsdt_applesmc_sta
#include "acpi-dsdt-isa.dsl"

676
hw/i386/acpi-dsdt.hex.generated
View File

@ -3,12 +3,12 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x53,
0x44,
0x54,
0x25,
0xe,
0x9a,
0xb,
0x0,
0x0,
0x1,
0x6c,
0xf8,
0x42,
0x58,
0x50,
@ -145,405 +145,6 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x44,
0x1,
0x10,
0x4e,
0x18,
0x2e,
0x5f,
0x53,
0x42,
0x5f,
0x50,
0x43,
0x49,
0x30,
0x8,
0x43,
0x52,
0x45,
0x53,
0x11,
0x42,
0xa,
0xa,
0x9e,
0x88,
0xd,
0x0,
0x2,
0xc,
0x0,
0x0,
0x0,
0x0,
0x0,
0xff,
0x0,
0x0,
0x0,
0x0,
0x1,
0x47,
0x1,
0xf8,
0xc,
0xf8,
0xc,
0x1,
0x8,
0x88,
0xd,
0x0,
0x1,
0xc,
0x3,
0x0,
0x0,
0x0,
0x0,
0xf7,
0xc,
0x0,
0x0,
0xf8,
0xc,
0x88,
0xd,
0x0,
0x1,
0xc,
0x3,
0x0,
0x0,
0x0,
0xd,
0xff,
0xad,
0x0,
0x0,
0x0,
0xa1,
0x88,
0xd,
0x0,
0x1,
0xc,
0x3,
0x0,
0x0,
0xf,
0xae,
0xff,
0xae,
0x0,
0x0,
0xf1,
0x0,
0x88,
0xd,
0x0,
0x1,
0xc,
0x3,
0x0,
0x0,
0x20,
0xaf,
0xdf,
0xaf,
0x0,
0x0,
0xc0,
0x0,
0x88,
0xd,
0x0,
0x1,
0xc,
0x3,
0x0,
0x0,
0xe4,
0xaf,
0xff,
0xff,
0x0,
0x0,
0x1c,
0x50,
0x87,
0x17,
0x0,
0x0,
0xc,
0x3,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0xa,
0x0,
0xff,
0xff,
0xb,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x2,
0x0,
0x87,
0x17,
0x0,
0x0,
0xc,
0x1,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0xe0,
0xff,
0xff,
0xbf,
0xfe,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0xc0,
0x1e,
0x79,
0x0,
0x8,
0x43,
0x52,
0x36,
0x34,
0x11,
0x33,
0xa,
0x30,
0x8a,
0x2b,
0x0,
0x0,
0xc,
0x3,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x80,
0x0,
0x0,
0x0,
0xff,
0xff,
0xff,
0xff,
0xff,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x80,
0x0,
0x0,
0x0,
0x79,
0x0,
0x14,
0x41,
0xa,
0x5f,
0x43,
0x52,
0x53,
0x0,
0x8a,
0x43,
0x52,
0x45,
0x53,
0xa,
0x8c,
0x50,
0x53,
0x33,
0x32,
0x8a,
0x43,
0x52,
0x45,
0x53,
0xa,
0x90,
0x50,
0x45,
0x33,
0x32,
0x8a,
0x43,
0x52,
0x45,
0x53,
0xa,
0x98,
0x50,
0x4c,
0x33,
0x32,
0x70,
0x50,
0x30,
0x53,
0x5f,
0x50,
0x53,
0x33,
0x32,
0x70,
0x50,
0x30,
0x45,
0x5f,
0x50,
0x45,
0x33,
0x32,
0x70,
0x72,
0x74,
0x50,
0x30,
0x45,
0x5f,
0x50,
0x30,
0x53,
0x5f,
0x0,
0x1,
0x0,
0x50,
0x4c,
0x33,
0x32,
0xa0,
0xc,
0x93,
0x50,
0x31,
0x56,
0x5f,
0x0,
0xa4,
0x43,
0x52,
0x45,
0x53,
0x8f,
0x43,
0x52,
0x36,
0x34,
0xa,
0xe,
0x50,
0x53,
0x36,
0x34,
0x8f,
0x43,
0x52,
0x36,
0x34,
0xa,
0x16,
0x50,
0x45,
0x36,
0x34,
0x8f,
0x43,
0x52,
0x36,
0x34,
0xa,
0x26,
0x50,
0x4c,
0x36,
0x34,
0x70,
0x50,
0x31,
0x53,
0x5f,
0x50,
0x53,
0x36,
0x34,
0x70,
0x50,
0x31,
0x45,
0x5f,
0x50,
0x45,
0x36,
0x34,
0x70,
0x50,
0x31,
0x4c,
0x5f,
0x50,
0x4c,
0x36,
0x34,
0x84,
0x43,
0x52,
0x45,
0x53,
0x43,
0x52,
0x36,
0x34,
0x60,
0xa4,
0x60,
0x10,
0x4d,
0x8,
0x5f,
@ -811,8 +412,8 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x4e,
0x1,
0x10,
0x4a,
0x1e,
0x4c,
0x1b,
0x2f,
0x3,
0x5f,
@ -829,52 +430,6 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x5f,
0x5b,
0x82,
0x2c,
0x53,
0x4d,
0x43,
0x5f,
0x8,
0x5f,
0x48,
0x49,
0x44,
0xc,
0x6,
0x10,
0x0,
0x1,
0x8,
0x5f,
0x53,
0x54,
0x41,
0xa,
0xf0,
0x8,
0x5f,
0x43,
0x52,
0x53,
0x11,
0x10,
0xa,
0xd,
0x47,
0x1,
0x0,
0x3,
0x0,
0x3,
0x1,
0x20,
0x22,
0x40,
0x0,
0x79,
0x0,
0x5b,
0x82,
0x2d,
0x52,
0x54,
@ -2318,8 +1873,8 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x53,
0x1,
0x10,
0x4f,
0x12,
0x4d,
0xc,
0x5f,
0x53,
0x42,
@ -2416,32 +1971,6 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x22,
0xa,
0xc8,
0x5b,
0x80,
0x50,
0x52,
0x53,
0x54,
0x1,
0xb,
0x0,
0xaf,
0xa,
0x20,
0x5b,
0x81,
0xc,
0x50,
0x52,
0x53,
0x54,
0x1,
0x50,
0x52,
0x53,
0x5f,
0x40,
0x10,
0x14,
0x4a,
0x6,
@ -2549,81 +2078,9 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x3,
0x75,
0x60,
0x5b,
0x82,
0x46,
0x4,
0x50,
0x52,
0x45,
0x53,
0x8,
0x5f,
0x48,
0x49,
0x44,
0xc,
0x41,
0xd0,
0xa,
0x6,
0x8,
0x5f,
0x55,
0x49,
0x44,
0xd,
0x43,
0x50,
0x55,
0x20,
0x68,
0x6f,
0x74,
0x70,
0x6c,
0x75,
0x67,
0x20,
0x72,
0x65,
0x73,
0x6f,
0x75,
0x72,
0x63,
0x65,
0x73,
0x0,
0x8,
0x5f,
0x43,
0x52,
0x53,
0x11,
0xd,
0xa,
0xa,
0x47,
0x1,
0x0,
0xaf,
0x0,
0xaf,
0x0,
0x20,
0x79,
0x0,
0x8,
0x5f,
0x53,
0x54,
0x41,
0xa,
0xb,
0x10,
0x40,
0x31,
0x44,
0x2a,
0x2e,
0x5f,
0x53,
@ -2635,8 +2092,8 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x30,
0x5b,
0x82,
0x43,
0x30,
0x47,
0x29,
0x4d,
0x48,
0x50,
@ -2686,37 +2143,6 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x65,
0x73,
0x0,
0x5b,
0x80,
0x48,
0x50,
0x4d,
0x52,
0x1,
0xb,
0x0,
0xa,
0xa,
0x18,
0x8,
0x5f,
0x43,
0x52,
0x53,
0x11,
0xd,
0xa,
0xa,
0x47,
0x1,
0x0,
0xa,
0x0,
0xa,
0x0,
0x18,
0x79,
0x0,
0x14,
0x13,
0x5f,
@ -2738,89 +2164,12 @@ static unsigned char AcpiDsdtAmlCode[] = {
0xa,
0xb,
0x5b,
0x81,
0x1f,
0x48,
0x50,
0x4d,
0x52,
0x3,
0x4d,
0x52,
0x42,
0x4c,
0x20,
0x4d,
0x52,
0x42,
0x48,
0x20,
0x4d,
0x52,
0x4c,
0x4c,
0x20,
0x4d,
0x52,
0x4c,
0x48,
0x20,
0x4d,
0x50,
0x58,
0x5f,
0x20,
0x5b,
0x81,
0x13,
0x48,
0x50,
0x4d,
0x52,
0x1,
0x0,
0x40,
0xa,
0x4d,
0x45,
0x53,
0x5f,
0x1,
0x4d,
0x49,
0x4e,
0x53,
0x1,
0x5b,
0x1,
0x4d,
0x4c,
0x43,
0x4b,
0x0,
0x5b,
0x81,
0x15,
0x48,
0x50,
0x4d,
0x52,
0x3,
0x4d,
0x53,
0x45,
0x4c,
0x20,
0x4d,
0x4f,
0x45,
0x56,
0x20,
0x4d,
0x4f,
0x53,
0x43,
0x20,
0x14,
0x4a,
0x4,
@ -3621,6 +2970,3 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x46,
0x0
};
static unsigned short piix_dsdt_applesmc_sta[] = {
0x353
};

10
hw/i386/kvm/pci-assign.c
View File

@ -1738,7 +1738,7 @@ static void reset_assigned_device(DeviceState *dev)
assigned_dev_pci_write_config(pci_dev, PCI_COMMAND, 0, 1);
}
static int assigned_initfn(struct PCIDevice *pci_dev)
static void assigned_realize(struct PCIDevice *pci_dev, Error **errp)
{
AssignedDevice *dev = DO_UPCAST(AssignedDevice, dev, pci_dev);
uint8_t e_intx;
@ -1821,7 +1821,7 @@ static int assigned_initfn(struct PCIDevice *pci_dev)
assigned_dev_load_option_rom(dev);
return 0;
return;
assigned_out:
deassign_device(dev);
@ -1831,9 +1831,7 @@ out:
exit_with_error:
assert(local_err);
qerror_report_err(local_err);
error_free(local_err);
return -1;
error_propagate(errp, local_err);
}
static void assigned_exitfn(struct PCIDevice *pci_dev)
@ -1869,7 +1867,7 @@ static void assign_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = assigned_initfn;
k->realize = assigned_realize;
k->exit = assigned_exitfn;
k->config_read = assigned_dev_pci_read_config;
k->config_write = assigned_dev_pci_write_config;

23
hw/i386/pc.c
View File

@ -1241,6 +1241,13 @@ FWCfgState *pc_memory_init(MachineState *machine,
exit(EXIT_FAILURE);
}
if (QEMU_ALIGN_UP(machine->maxram_size,
TARGET_PAGE_SIZE) != machine->maxram_size) {
error_report("maximum memory size must by aligned to multiple of "
"%d bytes", TARGET_PAGE_SIZE);
exit(EXIT_FAILURE);
}
pcms->hotplug_memory_base =
ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30);
@ -1666,6 +1673,20 @@ static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
}
}
static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
error_setg(errp, "acpi: device unplug request for not supported device"
" type: %s", object_get_typename(OBJECT(dev)));
}
static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
error_setg(errp, "acpi: device unplug for not supported device"
" type: %s", object_get_typename(OBJECT(dev)));
}
static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
DeviceState *dev)
{
@ -1795,6 +1816,8 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
pcmc->get_hotplug_handler = mc->get_hotplug_handler;
mc->get_hotplug_handler = pc_get_hotpug_handler;
hc->plug = pc_machine_device_plug_cb;
hc->unplug_request = pc_machine_device_unplug_request_cb;
hc->unplug = pc_machine_device_unplug_cb;
}
static const TypeInfo pc_machine_info = {

3
hw/i386/pc_piix.c
View File

@ -60,6 +60,7 @@ static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
static bool has_acpi_build = true;
static bool rsdp_in_ram = true;
static int legacy_acpi_table_size;
static bool smbios_defaults = true;
static bool smbios_legacy_mode;
@ -168,6 +169,7 @@ static void pc_init1(MachineState *machine,
guest_info->isapc_ram_fw = !pci_enabled;
guest_info->has_reserved_memory = has_reserved_memory;
guest_info->rsdp_in_ram = rsdp_in_ram;
if (smbios_defaults) {
MachineClass *mc = MACHINE_GET_CLASS(machine);
@ -310,6 +312,7 @@ static void pc_init_pci(MachineState *machine)
static void pc_compat_2_2(MachineState *machine)
{
rsdp_in_ram = false;
x86_cpu_compat_set_features("kvm64", FEAT_1_EDX, 0, CPUID_VME);
x86_cpu_compat_set_features("kvm32", FEAT_1_EDX, 0, CPUID_VME);
x86_cpu_compat_set_features("Conroe", FEAT_1_EDX, 0, CPUID_VME);

3
hw/i386/pc_q35.c
View File

@ -50,6 +50,7 @@
#define MAX_SATA_PORTS 6
static bool has_acpi_build = true;
static bool rsdp_in_ram = true;
static bool smbios_defaults = true;
static bool smbios_legacy_mode;
static bool smbios_uuid_encoded = true;
@ -154,6 +155,7 @@ static void pc_q35_init(MachineState *machine)
guest_info->isapc_ram_fw = false;
guest_info->has_acpi_build = has_acpi_build;
guest_info->has_reserved_memory = has_reserved_memory;
guest_info->rsdp_in_ram = rsdp_in_ram;
/* Migration was not supported in 2.0 for Q35, so do not bother
* with this hack (see hw/i386/acpi-build.c).
@ -289,6 +291,7 @@ static void pc_q35_init(MachineState *machine)
static void pc_compat_2_2(MachineState *machine)
{
rsdp_in_ram = false;
x86_cpu_compat_set_features("kvm64", FEAT_1_EDX, 0, CPUID_VME);
x86_cpu_compat_set_features("kvm32", FEAT_1_EDX, 0, CPUID_VME);
x86_cpu_compat_set_features("Conroe", FEAT_1_EDX, 0, CPUID_VME);

19
hw/i386/q35-acpi-dsdt.dsl
View File

@ -48,23 +48,6 @@ DefinitionBlock (
/****************************************************************
* PCI Bus definition
****************************************************************/
#define BOARD_SPECIFIC_PCI_RESOURSES \
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
0x0000, \
0x0000, \
0x0CD7, \
0x0000, \
0x0CD8, \
,, , TypeStatic) \
/* 0xcd8-0xcf7 hole for CPU hotplug, hw/acpi/ich9.c:ICH9_PROC_BASE */ \
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
0x0000, \
0x0D00, \
0xFFFF, \
0x0000, \
0xF300, \
,, , TypeStatic)
Scope(\_SB) {
Device(PCI0) {
Name(_HID, EisaId("PNP0A08"))
@ -131,7 +114,6 @@ DefinitionBlock (
}
}
#include "acpi-dsdt-pci-crs.dsl"
#include "acpi-dsdt-hpet.dsl"
@ -168,7 +150,6 @@ DefinitionBlock (
}
}
#define DSDT_APPLESMC_STA q35_dsdt_applesmc_sta
#include "acpi-dsdt-isa.dsl"

628
hw/i386/q35-acpi-dsdt.hex.generated
View File

@ -3,12 +3,12 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x53,
0x44,
0x54,
0x13,
0x20,
0xb8,
0x1d,
0x0,
0x0,
0x1,
0x0,
0x35,
0x42,
0x58,
0x50,
@ -360,357 +360,6 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0xa4,
0x6b,
0x10,
0x4e,
0x15,
0x2e,
0x5f,
0x53,
0x42,
0x5f,
0x50,
0x43,
0x49,
0x30,
0x8,
0x43,
0x52,
0x45,
0x53,
0x11,
0x42,
0x7,
0xa,
0x6e,
0x88,
0xd,
0x0,
0x2,
0xc,
0x0,
0x0,
0x0,
0x0,
0x0,
0xff,
0x0,
0x0,
0x0,
0x0,
0x1,
0x47,
0x1,
0xf8,
0xc,
0xf8,
0xc,
0x1,
0x8,
0x88,
0xd,
0x0,
0x1,
0xc,
0x3,
0x0,
0x0,
0x0,
0x0,
0xd7,
0xc,
0x0,
0x0,
0xd8,
0xc,
0x88,
0xd,
0x0,
0x1,
0xc,
0x3,
0x0,
0x0,
0x0,
0xd,
0xff,
0xff,
0x0,
0x0,
0x0,
0xf3,
0x87,
0x17,
0x0,
0x0,
0xc,
0x3,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0xa,
0x0,
0xff,
0xff,
0xb,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x2,
0x0,
0x87,
0x17,
0x0,
0x0,
0xc,
0x1,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0xe0,
0xff,
0xff,
0xbf,
0xfe,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0xc0,
0x1e,
0x79,
0x0,
0x8,
0x43,
0x52,
0x36,
0x34,
0x11,
0x33,
0xa,
0x30,
0x8a,
0x2b,
0x0,
0x0,
0xc,
0x3,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x80,
0x0,
0x0,
0x0,
0xff,
0xff,
0xff,
0xff,
0xff,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x80,
0x0,
0x0,
0x0,
0x79,
0x0,
0x14,
0x41,
0xa,
0x5f,
0x43,
0x52,
0x53,
0x0,
0x8a,
0x43,
0x52,
0x45,
0x53,
0xa,
0x5c,
0x50,
0x53,
0x33,
0x32,
0x8a,
0x43,
0x52,
0x45,
0x53,
0xa,
0x60,
0x50,
0x45,
0x33,
0x32,
0x8a,
0x43,
0x52,
0x45,
0x53,
0xa,
0x68,
0x50,
0x4c,
0x33,
0x32,
0x70,
0x50,
0x30,
0x53,
0x5f,
0x50,
0x53,
0x33,
0x32,
0x70,
0x50,
0x30,
0x45,
0x5f,
0x50,
0x45,
0x33,
0x32,
0x70,
0x72,
0x74,
0x50,
0x30,
0x45,
0x5f,
0x50,
0x30,
0x53,
0x5f,
0x0,
0x1,
0x0,
0x50,
0x4c,
0x33,
0x32,
0xa0,
0xc,
0x93,
0x50,
0x31,
0x56,
0x5f,
0x0,
0xa4,
0x43,
0x52,
0x45,
0x53,
0x8f,
0x43,
0x52,
0x36,
0x34,
0xa,
0xe,
0x50,
0x53,
0x36,
0x34,
0x8f,
0x43,
0x52,
0x36,
0x34,
0xa,
0x16,
0x50,
0x45,
0x36,
0x34,
0x8f,
0x43,
0x52,
0x36,
0x34,
0xa,
0x26,
0x50,
0x4c,
0x36,
0x34,
0x70,
0x50,
0x31,
0x53,
0x5f,
0x50,
0x53,
0x36,
0x34,
0x70,
0x50,
0x31,
0x45,
0x5f,
0x50,
0x45,
0x36,
0x34,
0x70,
0x50,
0x31,
0x4c,
0x5f,
0x50,
0x4c,
0x36,
0x34,
0x84,
0x43,
0x52,
0x45,
0x53,
0x43,
0x52,
0x36,
0x34,
0x60,
0xa4,
0x60,
0x10,
0x4d,
0x8,
0x5f,
@ -978,8 +627,8 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x4e,
0x1,
0x10,
0x4a,
0x1e,
0x4c,
0x1b,
0x2f,
0x3,
0x5f,
@ -996,52 +645,6 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x5f,
0x5b,
0x82,
0x2c,
0x53,
0x4d,
0x43,
0x5f,
0x8,
0x5f,
0x48,
0x49,
0x44,
0xc,
0x6,
0x10,
0x0,
0x1,
0x8,
0x5f,
0x53,
0x54,
0x41,
0xa,
0xf0,
0x8,
0x5f,
0x43,
0x52,
0x53,
0x11,
0x10,
0xa,
0xd,
0x47,
0x1,
0x0,
0x3,
0x0,
0x3,
0x1,
0x20,
0x22,
0x40,
0x0,
0x79,
0x0,
0x5b,
0x82,
0x2d,
0x52,
0x54,
@ -6959,8 +6562,8 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x53,
0x1,
0x10,
0x4f,
0x12,
0x4d,
0xc,
0x5f,
0x53,
0x42,
@ -7057,32 +6660,6 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x22,
0xa,
0xc8,
0x5b,
0x80,
0x50,
0x52,
0x53,
0x54,
0x1,
0xb,
0xd8,
0xc,
0xa,
0x20,
0x5b,
0x81,
0xc,
0x50,
0x52,
0x53,
0x54,
0x1,
0x50,
0x52,
0x53,
0x5f,
0x40,
0x10,
0x14,
0x4a,
0x6,
@ -7190,81 +6767,9 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x3,
0x75,
0x60,
0x5b,
0x82,
0x46,
0x4,
0x50,
0x52,
0x45,
0x53,
0x8,
0x5f,
0x48,
0x49,
0x44,
0xc,
0x41,
0xd0,
0xa,
0x6,
0x8,
0x5f,
0x55,
0x49,
0x44,
0xd,
0x43,
0x50,
0x55,
0x20,
0x68,
0x6f,
0x74,
0x70,
0x6c,
0x75,
0x67,
0x20,
0x72,
0x65,
0x73,
0x6f,
0x75,
0x72,
0x63,
0x65,
0x73,
0x0,
0x8,
0x5f,
0x43,
0x52,
0x53,
0x11,
0xd,
0xa,
0xa,
0x47,
0x1,
0xd8,
0xc,
0xd8,
0xc,
0x0,
0x20,
0x79,
0x0,
0x8,
0x5f,
0x53,
0x54,
0x41,
0xa,
0xb,
0x10,
0x40,
0x31,
0x44,
0x2a,
0x2e,
0x5f,
0x53,
@ -7276,8 +6781,8 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x30,
0x5b,
0x82,
0x43,
0x30,
0x47,
0x29,
0x4d,
0x48,
0x50,
@ -7327,37 +6832,6 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x65,
0x73,
0x0,
0x5b,
0x80,
0x48,
0x50,
0x4d,
0x52,
0x1,
0xb,
0x0,
0xa,
0xa,
0x18,
0x8,
0x5f,
0x43,
0x52,
0x53,
0x11,
0xd,
0xa,
0xa,
0x47,
0x1,
0x0,
0xa,
0x0,
0xa,
0x0,
0x18,
0x79,
0x0,
0x14,
0x13,
0x5f,
@ -7379,89 +6853,12 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0xa,
0xb,
0x5b,
0x81,
0x1f,
0x48,
0x50,
0x4d,
0x52,
0x3,
0x4d,
0x52,
0x42,
0x4c,
0x20,
0x4d,
0x52,
0x42,
0x48,
0x20,
0x4d,
0x52,
0x4c,
0x4c,
0x20,
0x4d,
0x52,
0x4c,
0x48,
0x20,
0x4d,
0x50,
0x58,
0x5f,
0x20,
0x5b,
0x81,
0x13,
0x48,
0x50,
0x4d,
0x52,
0x1,
0x0,
0x40,
0xa,
0x4d,
0x45,
0x53,
0x5f,
0x1,
0x4d,
0x49,
0x4e,
0x53,
0x1,
0x5b,
0x1,
0x4d,
0x4c,
0x43,
0x4b,
0x0,
0x5b,
0x81,
0x15,
0x48,
0x50,
0x4d,
0x52,
0x3,
0x4d,
0x53,
0x45,
0x4c,
0x20,
0x4d,
0x4f,
0x45,
0x56,
0x20,
0x4d,
0x4f,
0x53,
0x43,
0x20,
0x14,
0x4a,
0x4,
@ -8211,6 +7608,3 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x46,
0x0
};
static unsigned short q35_dsdt_applesmc_sta[] = {
0x3fa
};

77
hw/i386/ssdt-mem.dsl
View File

@ -1,77 +0,0 @@
/*
* Memory hotplug ACPI DSDT static objects definitions
*
* Copyright ProfitBricks GmbH 2012
* Copyright (C) 2013-2014 Red Hat Inc
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>
*/
/* This file is the basis for the ssdt_mem[] variable in src/acpi.c.
* It defines the contents of the memory device object. At
* runtime, a dynamically generated SSDT will contain one copy of this
* AML snippet for every possible memory device in the system. The
* objects will be placed in the \_SB_ namespace.
*
* In addition to the aml code generated from this file, the
* src/acpi.c file creates a MTFY method with an entry for each memdevice:
* Method(MTFY, 2) {
* If (LEqual(Arg0, 0x00)) { Notify(MP00, Arg1) }
* If (LEqual(Arg0, 0x01)) { Notify(MP01, Arg1) }
* ...
* }
*/
#include "hw/acpi/pc-hotplug.h"
ACPI_EXTRACT_ALL_CODE ssdm_mem_aml
DefinitionBlock ("ssdt-mem.aml", "SSDT", 0x02, "BXPC", "CSSDT", 0x1)
{
External(\_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_CRS_METHOD, MethodObj)
External(\_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_STATUS_METHOD, MethodObj)
External(\_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_OST_METHOD, MethodObj)
External(\_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_PROXIMITY_METHOD, MethodObj)
Scope(\_SB) {
/* v------------------ DO NOT EDIT ------------------v */
ACPI_EXTRACT_DEVICE_START ssdt_mem_start
ACPI_EXTRACT_DEVICE_END ssdt_mem_end
ACPI_EXTRACT_DEVICE_STRING ssdt_mem_name
Device(MPAA) {
ACPI_EXTRACT_NAME_STRING ssdt_mem_id
Name(_UID, "0xAA")
/* ^------------------ DO NOT EDIT ------------------^
* Don't change the above without also updating the C code.
*/
Name(_HID, EISAID("PNP0C80"))
Method(_CRS, 0) {
Return(\_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_CRS_METHOD(_UID))
}
Method(_STA, 0) {
Return(\_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_STATUS_METHOD(_UID))
}
Method(_PXM, 0) {
Return(\_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_PROXIMITY_METHOD(_UID))
}
Method(_OST, 3) {
\_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_OST_METHOD(_UID, Arg0, Arg1, Arg2)
}
}
}
}

213
hw/i386/ssdt-mem.hex.generated
View File

@ -1,213 +0,0 @@
static unsigned char ssdt_mem_id[] = {
0x35
};
static unsigned char ssdm_mem_aml[] = {
0x53,
0x53,
0x44,
0x54,
0xc7,
0x0,
0x0,
0x0,
0x2,
0x66,
0x42,
0x58,
0x50,
0x43,
0x0,
0x0,
0x43,
0x53,
0x53,
0x44,
0x54,
0x0,
0x0,
0x0,
0x1,
0x0,
0x0,
0x0,
0x49,
0x4e,
0x54,
0x4c,
0x28,
0x8,
0x14,
0x20,
0x10,
0x42,
0xa,
0x5c,
0x5f,
0x53,
0x42,
0x5f,
0x5b,
0x82,
0x49,
0x9,
0x4d,
0x50,
0x41,
0x41,
0x8,
0x5f,
0x55,
0x49,
0x44,
0xd,
0x30,
0x78,
0x41,
0x41,
0x0,
0x8,
0x5f,
0x48,
0x49,
0x44,
0xc,
0x41,
0xd0,
0xc,
0x80,
0x14,
0x1e,
0x5f,
0x43,
0x52,
0x53,
0x0,
0xa4,
0x5c,
0x2f,
0x4,
0x5f,
0x53,
0x42,
0x5f,
0x50,
0x43,
0x49,
0x30,
0x4d,
0x48,
0x50,
0x44,
0x4d,
0x43,
0x52,
0x53,
0x5f,
0x55,
0x49,
0x44,
0x14,
0x1e,
0x5f,
0x53,
0x54,
0x41,
0x0,
0xa4,
0x5c,
0x2f,
0x4,
0x5f,
0x53,
0x42,
0x5f,
0x50,
0x43,
0x49,
0x30,
0x4d,
0x48,
0x50,
0x44,
0x4d,
0x52,
0x53,
0x54,
0x5f,
0x55,
0x49,
0x44,
0x14,
0x1e,
0x5f,
0x50,
0x58,
0x4d,
0x0,
0xa4,
0x5c,
0x2f,
0x4,
0x5f,
0x53,
0x42,
0x5f,
0x50,
0x43,
0x49,
0x30,
0x4d,
0x48,
0x50,
0x44,
0x4d,
0x50,
0x58,
0x4d,
0x5f,
0x55,
0x49,
0x44,
0x14,
0x20,
0x5f,
0x4f,
0x53,
0x54,
0x3,
0x5c,
0x2f,
0x4,
0x5f,
0x53,
0x42,
0x5f,
0x50,
0x43,
0x49,
0x30,
0x4d,
0x48,
0x50,
0x44,
0x4d,
0x4f,
0x53,
0x54,
0x5f,
0x55,
0x49,
0x44,
0x68,
0x69,
0x6a
};
static unsigned char ssdt_mem_start[] = {
0x2c
};
static unsigned char ssdt_mem_end[] = {
0xc7
};
static unsigned char ssdt_mem_name[] = {
0x30
};

122
hw/i386/ssdt-misc.dsl
View File

@ -1,122 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "hw/acpi/pc-hotplug.h"
ACPI_EXTRACT_ALL_CODE ssdp_misc_aml
DefinitionBlock ("ssdt-misc.aml", "SSDT", 0x01, "BXPC", "BXSSDTSUSP", 0x1)
{
/****************************************************************
* PCI memory ranges
****************************************************************/
Scope(\) {
ACPI_EXTRACT_NAME_DWORD_CONST acpi_pci32_start
Name(P0S, 0x12345678)
ACPI_EXTRACT_NAME_DWORD_CONST acpi_pci32_end
Name(P0E, 0x12345678)
ACPI_EXTRACT_NAME_BYTE_CONST acpi_pci64_valid
Name(P1V, 0x12)
ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_start
Name(P1S, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_end
Name(P1E, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_length
Name(P1L, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
ACPI_EXTRACT_NAME_DWORD_CONST ssdt_mctrl_nr_slots
Name(MEMORY_SLOTS_NUMBER, 0x12345678)
}
/****************************************************************
* Suspend
****************************************************************/
Scope(\) {
/*
* S3 (suspend-to-ram), S4 (suspend-to-disk) and S5 (power-off) type codes:
* must match piix4 emulation.
*/
ACPI_EXTRACT_NAME_STRING acpi_s3_name
Name(_S3, Package(0x04) {
One, /* PM1a_CNT.SLP_TYP */
One, /* PM1b_CNT.SLP_TYP */
Zero, /* reserved */
Zero /* reserved */
})
ACPI_EXTRACT_NAME_STRING acpi_s4_name
ACPI_EXTRACT_PKG_START acpi_s4_pkg
Name(_S4, Package(0x04) {
0x2, /* PM1a_CNT.SLP_TYP */
0x2, /* PM1b_CNT.SLP_TYP */
Zero, /* reserved */
Zero /* reserved */
})
Name(_S5, Package(0x04) {
Zero, /* PM1a_CNT.SLP_TYP */
Zero, /* PM1b_CNT.SLP_TYP */
Zero, /* reserved */
Zero /* reserved */
})
}
External(\_SB.PCI0, DeviceObj)
External(\_SB.PCI0.ISA, DeviceObj)
Scope(\_SB.PCI0.ISA) {
Device(PEVT) {
Name(_HID, "QEMU0001")
/* PEST will be patched to be Zero if no such device */
ACPI_EXTRACT_NAME_WORD_CONST ssdt_isa_pest
Name(PEST, 0xFFFF)
OperationRegion(PEOR, SystemIO, PEST, 0x01)
Field(PEOR, ByteAcc, NoLock, Preserve) {
PEPT, 8,
}
Method(_STA, 0, NotSerialized) {
Store(PEST, Local0)
If (LEqual(Local0, Zero)) {
Return (0x00)
} Else {
Return (0x0F)
}
}
Method(RDPT, 0, NotSerialized) {
Store(PEPT, Local0)
Return (Local0)
}
Method(WRPT, 1, NotSerialized) {
Store(Arg0, PEPT)
}
Name(_CRS, ResourceTemplate() {
IO(Decode16, 0x00, 0x00, 0x01, 0x01, IO)
})
CreateWordField(_CRS, IO._MIN, IOMN)
CreateWordField(_CRS, IO._MAX, IOMX)
Method(_INI, 0, NotSerialized) {
Store(PEST, IOMN)
Store(PEST, IOMX)
}
}
}
}

399
hw/i386/ssdt-misc.hex.generated
View File

@ -1,399 +0,0 @@
static unsigned char acpi_pci64_length[] = {
0x6f
};
static unsigned char acpi_s4_pkg[] = {
0x99
};
static unsigned char ssdt_mctrl_nr_slots[] = {
0x7d
};
static unsigned char acpi_s3_name[] = {
0x86
};
static unsigned char acpi_pci32_start[] = {
0x2f
};
static unsigned char acpi_pci64_valid[] = {
0x43
};
static unsigned char ssdp_misc_aml[] = {
0x53,
0x53,
0x44,
0x54,
0x6c,
0x1,
0x0,
0x0,
0x1,
0x3,
0x42,
0x58,
0x50,
0x43,
0x0,
0x0,
0x42,
0x58,
0x53,
0x53,
0x44,
0x54,
0x53,
0x55,
0x1,
0x0,
0x0,
0x0,
0x49,
0x4e,
0x54,
0x4c,
0x28,
0x8,
0x14,
0x20,
0x10,
0x4c,
0x5,
0x5c,
0x0,
0x8,
0x50,
0x30,
0x53,
0x5f,
0xc,
0x78,
0x56,
0x34,
0x12,
0x8,
0x50,
0x30,
0x45,
0x5f,
0xc,
0x78,
0x56,
0x34,
0x12,
0x8,
0x50,
0x31,
0x56,
0x5f,
0xa,
0x12,
0x8,
0x50,
0x31,
0x53,
0x5f,
0x11,
0xb,
0xa,
0x8,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x8,
0x50,
0x31,
0x45,
0x5f,
0x11,
0xb,
0xa,
0x8,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x8,
0x50,
0x31,
0x4c,
0x5f,
0x11,
0xb,
0xa,
0x8,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x8,
0x4d,
0x44,
0x4e,
0x52,
0xc,
0x78,
0x56,
0x34,
0x12,
0x10,
0x29,
0x5c,
0x0,
0x8,
0x5f,
0x53,
0x33,
0x5f,
0x12,
0x6,
0x4,
0x1,
0x1,
0x0,
0x0,
0x8,
0x5f,
0x53,
0x34,
0x5f,
0x12,
0x8,
0x4,
0xa,
0x2,
0xa,
0x2,
0x0,
0x0,
0x8,
0x5f,
0x53,
0x35,
0x5f,
0x12,
0x6,
0x4,
0x0,
0x0,
0x0,
0x0,
0x10,
0x40,
0xc,
0x5c,
0x2f,
0x3,
0x5f,
0x53,
0x42,
0x5f,
0x50,
0x43,
0x49,
0x30,
0x49,
0x53,
0x41,
0x5f,
0x5b,
0x82,
0x4d,
0xa,
0x50,
0x45,
0x56,
0x54,
0x8,
0x5f,
0x48,
0x49,
0x44,
0xd,
0x51,
0x45,
0x4d,
0x55,
0x30,
0x30,
0x30,
0x31,
0x0,
0x8,
0x50,
0x45,
0x53,
0x54,
0xb,
0xff,
0xff,
0x5b,
0x80,
0x50,
0x45,
0x4f,
0x52,
0x1,
0x50,
0x45,
0x53,
0x54,
0x1,
0x5b,
0x81,
0xb,
0x50,
0x45,
0x4f,
0x52,
0x1,
0x50,
0x45,
0x50,
0x54,
0x8,
0x14,
0x18,
0x5f,
0x53,
0x54,
0x41,
0x0,
0x70,
0x50,
0x45,
0x53,
0x54,
0x60,
0xa0,
0x6,
0x93,
0x60,
0x0,
0xa4,
0x0,
0xa1,
0x4,
0xa4,
0xa,
0xf,
0x14,
0xe,
0x52,
0x44,
0x50,
0x54,
0x0,
0x70,
0x50,
0x45,
0x50,
0x54,
0x60,
0xa4,
0x60,
0x14,
0xc,
0x57,
0x52,
0x50,
0x54,
0x1,
0x70,
0x68,
0x50,
0x45,
0x50,
0x54,
0x8,
0x5f,
0x43,
0x52,
0x53,
0x11,
0xd,
0xa,
0xa,
0x47,
0x1,
0x0,
0x0,
0x0,
0x0,
0x1,
0x1,
0x79,
0x0,
0x8b,
0x5f,
0x43,
0x52,
0x53,
0xa,
0x2,
0x49,
0x4f,
0x4d,
0x4e,
0x8b,
0x5f,
0x43,
0x52,
0x53,
0xa,
0x4,
0x49,
0x4f,
0x4d,
0x58,
0x14,
0x18,
0x5f,
0x49,
0x4e,
0x49,
0x0,
0x70,
0x50,
0x45,
0x53,
0x54,
0x49,
0x4f,
0x4d,
0x4e,
0x70,
0x50,
0x45,
0x53,
0x54,
0x49,
0x4f,
0x4d,
0x58
};
static unsigned char ssdt_isa_pest[] = {
0xda
};
static unsigned char acpi_s4_name[] = {
0x92
};
static unsigned char acpi_pci64_start[] = {
0x4d
};
static unsigned char acpi_pci64_end[] = {
0x5e
};
static unsigned char acpi_pci32_end[] = {
0x39
};

100
hw/i386/ssdt-pcihp.dsl
View File

@ -1,100 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
ACPI_EXTRACT_ALL_CODE ssdp_pcihp_aml
DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
{
/****************************************************************
* PCI hotplug
****************************************************************/
/* Objects supplied by DSDT */
External(\_SB.PCI0, DeviceObj)
External(\_SB.PCI0.PCEJ, MethodObj)
External(BSEL, IntObj)
Scope(\_SB.PCI0) {
/* Bulk generated PCI hotplug devices */
ACPI_EXTRACT_DEVICE_START ssdt_pcihp_start
ACPI_EXTRACT_DEVICE_END ssdt_pcihp_end
ACPI_EXTRACT_DEVICE_STRING ssdt_pcihp_name
// Extract the offsets of the device name, address dword and the slot
// name byte - we fill them in for each device.
Device(SAA) {
ACPI_EXTRACT_NAME_BYTE_CONST ssdt_pcihp_id
Name(_SUN, 0xAA)
ACPI_EXTRACT_NAME_DWORD_CONST ssdt_pcihp_adr
Name(_ADR, 0xAA0000)
Method(_EJ0, 1) {
PCEJ(BSEL, _SUN)
}
}
ACPI_EXTRACT_DEVICE_START ssdt_pcinohp_start
ACPI_EXTRACT_DEVICE_END ssdt_pcinohp_end
ACPI_EXTRACT_DEVICE_STRING ssdt_pcinohp_name
// Extract the offsets of the device name, address dword and the slot
// name byte - we fill them in for each device.
Device(SBB) {
ACPI_EXTRACT_NAME_DWORD_CONST ssdt_pcinohp_adr
Name(_ADR, 0xAA0000)
}
ACPI_EXTRACT_DEVICE_START ssdt_pcivga_start
ACPI_EXTRACT_DEVICE_END ssdt_pcivga_end
ACPI_EXTRACT_DEVICE_STRING ssdt_pcivga_name
// Extract the offsets of the device name, address dword and the slot
// name byte - we fill them in for each device.
Device(SCC) {
ACPI_EXTRACT_NAME_DWORD_CONST ssdt_pcivga_adr
Name(_ADR, 0xAA0000)
Method(_S1D, 0, NotSerialized) {
Return (0x00)
}
Method(_S2D, 0, NotSerialized) {
Return (0x00)
}
Method(_S3D, 0, NotSerialized) {
Return (0x00)
}
}
ACPI_EXTRACT_DEVICE_START ssdt_pciqxl_start
ACPI_EXTRACT_DEVICE_END ssdt_pciqxl_end
ACPI_EXTRACT_DEVICE_STRING ssdt_pciqxl_name
// Extract the offsets of the device name, address dword and the slot
// name byte - we fill them in for each device.
Device(SDD) {
ACPI_EXTRACT_NAME_DWORD_CONST ssdt_pciqxl_adr
Name(_ADR, 0xAA0000)
Method(_S1D, 0, NotSerialized) {
Return (0x00)
}
Method(_S2D, 0, NotSerialized) {
Return (0x00)
}
Method(_S3D, 0, NotSerialized) {
Return (0x03) // QXL
}
}
}
}

251
hw/i386/ssdt-pcihp.hex.generated
View File

@ -1,251 +0,0 @@
static unsigned char ssdt_pcihp_name[] = {
0x34
};
static unsigned char ssdt_pcivga_end[] = {
0x99
};
static unsigned char ssdt_pcivga_name[] = {
0x70
};
static unsigned char ssdt_pcihp_adr[] = {
0x45
};
static unsigned char ssdt_pcinohp_end[] = {
0x6d
};
static unsigned char ssdt_pcihp_end[] = {
0x5c
};
static unsigned char ssdt_pciqxl_start[] = {
0x99
};
static unsigned char ssdt_pcinohp_name[] = {
0x5f
};
static unsigned char ssdp_pcihp_aml[] = {
0x53,
0x53,
0x44,
0x54,
0xc6,
0x0,
0x0,
0x0,
0x1,
0x70,
0x42,
0x58,
0x50,
0x43,
0x0,
0x0,
0x42,
0x58,
0x53,
0x53,
0x44,
0x54,
0x50,
0x43,
0x1,
0x0,
0x0,
0x0,
0x49,
0x4e,
0x54,
0x4c,
0x15,
0x11,
0x13,
0x20,
0x10,
0x41,
0xa,
0x5c,
0x2e,
0x5f,
0x53,
0x42,
0x5f,
0x50,
0x43,
0x49,
0x30,
0x5b,
0x82,
0x29,
0x53,
0x41,
0x41,
0x5f,
0x8,
0x5f,
0x53,
0x55,
0x4e,
0xa,
0xaa,
0x8,
0x5f,
0x41,
0x44,
0x52,
0xc,
0x0,
0x0,
0xaa,
0x0,
0x14,
0x12,
0x5f,
0x45,
0x4a,
0x30,
0x1,
0x50,
0x43,
0x45,
0x4a,
0x42,
0x53,
0x45,
0x4c,
0x5f,
0x53,
0x55,
0x4e,
0x5b,
0x82,
0xf,
0x53,
0x42,
0x42,
0x5f,
0x8,
0x5f,
0x41,
0x44,
0x52,
0xc,
0x0,
0x0,
0xaa,
0x0,
0x5b,
0x82,
0x2a,
0x53,
0x43,
0x43,
0x5f,
0x8,
0x5f,
0x41,
0x44,
0x52,
0xc,
0x0,
0x0,
0xaa,
0x0,
0x14,
0x8,
0x5f,
0x53,
0x31,
0x44,
0x0,
0xa4,
0x0,
0x14,
0x8,
0x5f,
0x53,
0x32,
0x44,
0x0,
0xa4,
0x0,
0x14,
0x8,
0x5f,
0x53,
0x33,
0x44,
0x0,
0xa4,
0x0,
0x5b,
0x82,
0x2b,
0x53,
0x44,
0x44,
0x5f,
0x8,
0x5f,
0x41,
0x44,
0x52,
0xc,
0x0,
0x0,
0xaa,
0x0,
0x14,
0x8,
0x5f,
0x53,
0x31,
0x44,
0x0,
0xa4,
0x0,
0x14,
0x8,
0x5f,
0x53,
0x32,
0x44,
0x0,
0xa4,
0x0,
0x14,
0x9,
0x5f,
0x53,
0x33,
0x44,
0x0,
0xa4,
0xa,
0x3
};
static unsigned char ssdt_pciqxl_adr[] = {
0xa6
};
static unsigned char ssdt_pcinohp_adr[] = {
0x69
};
static unsigned char ssdt_pcivga_adr[] = {
0x7a
};
static unsigned char ssdt_pciqxl_name[] = {
0x9c
};
static unsigned char ssdt_pcivga_start[] = {
0x6d
};
static unsigned char ssdt_pciqxl_end[] = {
0xc6
};
static unsigned char ssdt_pcihp_start[] = {
0x31
};
static unsigned char ssdt_pcihp_id[] = {
0x3e
};
static unsigned char ssdt_pcinohp_start[] = {
0x5c
};

63
hw/i386/ssdt-proc.dsl
View File

@ -1,63 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
/* This file is the basis for the ssdt table generated in src/acpi.c.
* It defines the contents of the per-cpu Processor() object. At
* runtime, a dynamically generated SSDT will contain one copy of this
* AML snippet for every possible cpu in the system. The objects will
* be placed in the \_SB_ namespace.
*
* In addition to the aml code generated from this file, the
* src/acpi.c file creates a NTFY method with an entry for each cpu:
* Method(NTFY, 2) {
* If (LEqual(Arg0, 0x00)) { Notify(CP00, Arg1) }
* If (LEqual(Arg0, 0x01)) { Notify(CP01, Arg1) }
* ...
* }
* and a CPON array with the list of active and inactive cpus:
* Name(CPON, Package() { One, One, ..., Zero, Zero, ... })
*/
ACPI_EXTRACT_ALL_CODE ssdp_proc_aml
DefinitionBlock ("ssdt-proc.aml", "SSDT", 0x01, "BXPC", "BXSSDT", 0x1)
{
ACPI_EXTRACT_PROCESSOR_START ssdt_proc_start
ACPI_EXTRACT_PROCESSOR_END ssdt_proc_end
ACPI_EXTRACT_PROCESSOR_STRING ssdt_proc_name
Processor(CPAA, 0xAA, 0x00000000, 0x0) {
ACPI_EXTRACT_NAME_BYTE_CONST ssdt_proc_id
Name(ID, 0xAA)
/*
* The src/acpi.c code requires the above ACP_EXTRACT tags so that it can update
* CPAA and 0xAA with the appropriate CPU id (see
* SD_OFFSET_CPUHEX/CPUID1/CPUID2). Don't change the above without
* also updating the C code.
*/
Name(_HID, "ACPI0007")
External(CPMA, MethodObj)
External(CPST, MethodObj)
External(CPEJ, MethodObj)
Method(_MAT, 0) {
Return (CPMA(ID))
}
Method(_STA, 0) {
Return (CPST(ID))
}
Method(_EJ0, 1, NotSerialized) {
CPEJ(ID, Arg0)
}
}
}

134
hw/i386/ssdt-proc.hex.generated
View File

@ -1,134 +0,0 @@
static unsigned char ssdt_proc_name[] = {
0x28
};
static unsigned char ssdp_proc_aml[] = {
0x53,
0x53,
0x44,
0x54,
0x78,
0x0,
0x0,
0x0,
0x1,
0x7d,
0x42,
0x58,
0x50,
0x43,
0x0,
0x0,
0x42,
0x58,
0x53,
0x53,
0x44,
0x54,
0x0,
0x0,
0x1,
0x0,
0x0,
0x0,
0x49,
0x4e,
0x54,
0x4c,
0x15,
0x11,
0x13,
0x20,
0x5b,
0x83,
0x42,
0x5,
0x43,
0x50,
0x41,
0x41,
0xaa,
0x0,
0x0,
0x0,
0x0,
0x0,
0x8,
0x49,
0x44,
0x5f,
0x5f,
0xa,
0xaa,
0x8,
0x5f,
0x48,
0x49,
0x44,
0xd,
0x41,
0x43,
0x50,
0x49,
0x30,
0x30,
0x30,
0x37,
0x0,
0x14,
0xf,
0x5f,
0x4d,
0x41,
0x54,
0x0,
0xa4,
0x43,
0x50,
0x4d,
0x41,
0x49,
0x44,
0x5f,
0x5f,
0x14,
0xf,
0x5f,
0x53,
0x54,
0x41,
0x0,
0xa4,
0x43,
0x50,
0x53,
0x54,
0x49,
0x44,
0x5f,
0x5f,
0x14,
0xf,
0x5f,
0x45,
0x4a,
0x30,
0x1,
0x43,
0x50,
0x45,
0x4a,
0x49,
0x44,
0x5f,
0x5f,
0x68
};
static unsigned char ssdt_proc_id[] = {
0x38
};
static unsigned char ssdt_proc_end[] = {
0x78
};
static unsigned char ssdt_proc_start[] = {
0x24
};

6
hw/i386/ssdt-tpm.hex.generated
View File

@ -8,7 +8,7 @@ static unsigned char ssdt_tpm_aml[] = {
0x0,
0x0,
0x1,
0xf,
0x1c,
0x42,
0x58,
0x50,
@ -31,9 +31,9 @@ static unsigned char ssdt_tpm_aml[] = {
0x4e,
0x54,
0x4c,
0x15,
0x7,
0x11,
0x13,
0x14,
0x20,
0x10,
0x38,

5
hw/ide/cmd646.c
View File

@ -326,7 +326,7 @@ static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
}
/* CMD646 PCI IDE controller */
static int pci_cmd646_ide_initfn(PCIDevice *dev)
static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
{
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
@ -374,7 +374,6 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
qemu_register_reset(cmd646_reset, d);
return 0;
}
static void pci_cmd646_ide_exitfn(PCIDevice *dev)
@ -410,7 +409,7 @@ static void cmd646_ide_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_cmd646_ide_initfn;
k->realize = pci_cmd646_ide_realize;
k->exit = pci_cmd646_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_CMD;
k->device_id = PCI_DEVICE_ID_CMD_646;

13
hw/ide/ich.c
View File

@ -98,7 +98,7 @@ static void pci_ich9_reset(DeviceState *dev)
ahci_reset(&d->ahci);
}
static int pci_ich9_ahci_init(PCIDevice *dev)
static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
{
struct AHCIPCIState *d;
int sata_cap_offset;
@ -123,10 +123,11 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
&d->ahci.mem);
sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA,
ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE);
sata_cap_offset = pci_add_capability2(dev, PCI_CAP_ID_SATA,
ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE,
errp);
if (sata_cap_offset < 0) {
return sata_cap_offset;
return;
}
sata_cap = dev->config + sata_cap_offset;
@ -139,8 +140,6 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
* should be PMCAP, the Intel ICH9 data sheet specifies that the ICH9
* AHCI device puts the MSI capability first, pointing to 0x80. */
msi_init(dev, ICH9_MSI_CAP_OFFSET, 1, true, false);
return 0;
}
static void pci_ich9_uninit(PCIDevice *dev)
@ -158,7 +157,7 @@ static void ich_ahci_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_ich9_ahci_init;
k->realize = pci_ich9_ahci_realize;
k->exit = pci_ich9_uninit;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82801IR;

10
hw/ide/piix.c
View File

@ -148,7 +148,7 @@ static void pci_piix_init_ports(PCIIDEState *d) {
}
}
static int pci_piix_ide_initfn(PCIDevice *dev)
static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
{
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
@ -163,8 +163,6 @@ static int pci_piix_ide_initfn(PCIDevice *dev)
vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
pci_piix_init_ports(d);
return 0;
}
int pci_piix3_xen_ide_unplug(DeviceState *dev)
@ -238,7 +236,7 @@ static void piix3_ide_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_piix_ide_initfn;
k->realize = pci_piix_ide_realize;
k->exit = pci_piix_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
@ -258,7 +256,7 @@ static void piix3_ide_xen_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_piix_ide_initfn;
k->realize = pci_piix_ide_realize;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
k->class_id = PCI_CLASS_STORAGE_IDE;
@ -276,7 +274,7 @@ static void piix4_ide_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_piix_ide_initfn;
k->realize = pci_piix_ide_realize;
k->exit = pci_piix_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371AB;

6
hw/ide/via.c
View File

@ -172,7 +172,7 @@ static void vt82c686b_init_ports(PCIIDEState *d) {
}
/* via ide func */
static int vt82c686b_ide_initfn(PCIDevice *dev)
static void vt82c686b_ide_realize(PCIDevice *dev, Error **errp)
{
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
@ -187,8 +187,6 @@ static int vt82c686b_ide_initfn(PCIDevice *dev)
vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
vt82c686b_init_ports(d);
return 0;
}
static void vt82c686b_ide_exitfn(PCIDevice *dev)
@ -215,7 +213,7 @@ static void via_ide_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = vt82c686b_ide_initfn;
k->realize = vt82c686b_ide_realize;
k->exit = vt82c686b_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_VIA;
k->device_id = PCI_DEVICE_ID_VIA_IDE;

6
hw/ipack/tpci200.c
View File

@ -573,7 +573,7 @@ static const MemoryRegionOps tpci200_las3_ops = {
}
};
static int tpci200_initfn(PCIDevice *pci_dev)
static void tpci200_realize(PCIDevice *pci_dev, Error **errp)
{
TPCI200State *s = TPCI200(pci_dev);
uint8_t *c = s->dev.config;
@ -609,8 +609,6 @@ static int tpci200_initfn(PCIDevice *pci_dev)
ipack_bus_new_inplace(&s->bus, sizeof(s->bus), DEVICE(pci_dev), NULL,
N_MODULES, tpci200_set_irq);
return 0;
}
static const VMStateDescription vmstate_tpci200 = {
@ -632,7 +630,7 @@ static void tpci200_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = tpci200_initfn;
k->realize = tpci200_realize;
k->vendor_id = PCI_VENDOR_ID_TEWS;
k->device_id = PCI_DEVICE_ID_TEWS_TPCI200;
k->class_id = PCI_CLASS_BRIDGE_OTHER;

6
hw/isa/i82378.c
View File

@ -58,7 +58,7 @@ static void i82378_request_pic_irq(void *opaque, int irq, int level)
qemu_set_irq(s->i8259[irq], level);
}
static int i82378_initfn(PCIDevice *pci)
static void i82378_realize(PCIDevice *pci, Error **errp)
{
DeviceState *dev = DEVICE(pci);
I82378State *s = I82378(dev);
@ -107,8 +107,6 @@ static int i82378_initfn(PCIDevice *pci)
/* timer */
isa_create_simple(isabus, "mc146818rtc");
return 0;
}
static void i82378_init(Object *obj)
@ -125,7 +123,7 @@ static void i82378_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = i82378_initfn;
k->realize = i82378_realize;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82378;
k->revision = 0x03;

14
hw/isa/lpc_ich9.c
View File

@ -610,8 +610,17 @@ static void ich9_device_plug_cb(HotplugHandler *hotplug_dev,
static void ich9_device_unplug_request_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
error_setg(errp, "acpi: device unplug request for not supported device"
" type: %s", object_get_typename(OBJECT(dev)));
ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
ich9_pm_device_unplug_request_cb(&lpc->pm, dev, errp);
}
static void ich9_device_unplug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
ich9_pm_device_unplug_cb(&lpc->pm, dev, errp);
}
static bool ich9_rst_cnt_needed(void *opaque)
@ -677,6 +686,7 @@ static void ich9_lpc_class_init(ObjectClass *klass, void *data)
dc->cannot_instantiate_with_device_add_yet = true;
hc->plug = ich9_device_plug_cb;
hc->unplug_request = ich9_device_unplug_request_cb;
hc->unplug = ich9_device_unplug_cb;
adevc->ospm_status = ich9_pm_ospm_status;
}

5
hw/isa/piix4.c
View File

@ -82,7 +82,7 @@ static const VMStateDescription vmstate_piix4 = {
}
};
static int piix4_initfn(PCIDevice *dev)
static void piix4_realize(PCIDevice *dev, Error **errp)
{
PIIX4State *d = DO_UPCAST(PIIX4State, dev, dev);
@ -90,7 +90,6 @@ static int piix4_initfn(PCIDevice *dev)
pci_address_space_io(dev));
piix4_dev = &d->dev;
qemu_register_reset(piix4_reset, d);
return 0;
}
int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
@ -107,7 +106,7 @@ static void piix4_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = piix4_initfn;
k->realize = piix4_realize;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
k->class_id = PCI_CLASS_BRIDGE_ISA;

24
hw/isa/vt82c686.c
View File

@ -245,7 +245,7 @@ static const VMStateDescription vmstate_acpi = {
* just register a PCI device now, functionalities will be implemented later.
*/
static int vt82c686b_ac97_initfn(PCIDevice *dev)
static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp)
{
VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
uint8_t *pci_conf = s->dev.config;
@ -255,8 +255,6 @@ static int vt82c686b_ac97_initfn(PCIDevice *dev)
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
PCI_STATUS_DEVSEL_MEDIUM);
pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
return 0;
}
void vt82c686b_ac97_init(PCIBus *bus, int devfn)
@ -272,7 +270,7 @@ static void via_ac97_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = vt82c686b_ac97_initfn;
k->realize = vt82c686b_ac97_realize;
k->vendor_id = PCI_VENDOR_ID_VIA;
k->device_id = PCI_DEVICE_ID_VIA_AC97;
k->revision = 0x50;
@ -288,7 +286,7 @@ static const TypeInfo via_ac97_info = {
.class_init = via_ac97_class_init,
};
static int vt82c686b_mc97_initfn(PCIDevice *dev)
static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp)
{
VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
uint8_t *pci_conf = s->dev.config;
@ -297,8 +295,6 @@ static int vt82c686b_mc97_initfn(PCIDevice *dev)
PCI_COMMAND_VGA_PALETTE);
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
return 0;
}
void vt82c686b_mc97_init(PCIBus *bus, int devfn)
@ -314,7 +310,7 @@ static void via_mc97_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = vt82c686b_mc97_initfn;
k->realize = vt82c686b_mc97_realize;
k->vendor_id = PCI_VENDOR_ID_VIA;
k->device_id = PCI_DEVICE_ID_VIA_MC97;
k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
@ -331,7 +327,7 @@ static const TypeInfo via_mc97_info = {
};
/* vt82c686 pm init */
static int vt82c686b_pm_initfn(PCIDevice *dev)
static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp)
{
VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
uint8_t *pci_conf;
@ -361,8 +357,6 @@ static int vt82c686b_pm_initfn(PCIDevice *dev)
acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
acpi_pm1_cnt_init(&s->ar, &s->io, 2);
return 0;
}
I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
@ -391,7 +385,7 @@ static void via_pm_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = vt82c686b_pm_initfn;
k->realize = vt82c686b_pm_realize;
k->config_write = pm_write_config;
k->vendor_id = PCI_VENDOR_ID_VIA;
k->device_id = PCI_DEVICE_ID_VIA_ACPI;
@ -421,7 +415,7 @@ static const VMStateDescription vmstate_via = {
};
/* init the PCI-to-ISA bridge */
static int vt82c686b_initfn(PCIDevice *d)
static void vt82c686b_realize(PCIDevice *d, Error **errp)
{
VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
uint8_t *pci_conf;
@ -451,8 +445,6 @@ static int vt82c686b_initfn(PCIDevice *d)
&vt82c->superio);
qemu_register_reset(vt82c686b_reset, d);
return 0;
}
ISABus *vt82c686b_init(PCIBus *bus, int devfn)
@ -469,7 +461,7 @@ static void via_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = vt82c686b_initfn;
k->realize = vt82c686b_realize;
k->config_write = vt82c686b_write_config;
k->vendor_id = PCI_VENDOR_ID_VIA;
k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;

5
hw/misc/applesmc.c
View File

@ -43,7 +43,6 @@
/* command/status port used by Apple SMC */
#define APPLESMC_CMD_PORT 0x4
#define APPLESMC_NR_PORTS 32
#define APPLESMC_MAX_DATA_LENGTH 32
#define APPLESMC_READ_CMD 0x10
#define APPLESMC_WRITE_CMD 0x11
@ -249,8 +248,8 @@ static void applesmc_isa_realize(DeviceState *dev, Error **errp)
}
static Property applesmc_isa_properties[] = {
DEFINE_PROP_UINT32("iobase", AppleSMCState, iobase,
APPLESMC_DEFAULT_IOBASE),
DEFINE_PROP_UINT32(APPLESMC_PROP_IO_BASE, AppleSMCState, iobase,
APPLESMC_DEFAULT_IOBASE),
DEFINE_PROP_STRING("osk", AppleSMCState, osk),
DEFINE_PROP_END_OF_LIST(),
};

6
hw/misc/pci-testdev.c
View File

@ -233,7 +233,7 @@ static const MemoryRegionOps pci_testdev_pio_ops = {
},
};
static int pci_testdev_init(PCIDevice *pci_dev)
static void pci_testdev_realize(PCIDevice *pci_dev, Error **errp)
{
PCITestDevState *d = PCI_TEST_DEV(pci_dev);
uint8_t *pci_conf;
@ -275,8 +275,6 @@ static int pci_testdev_init(PCIDevice *pci_dev)
assert(r >= 0);
test->hasnotifier = true;
}
return 0;
}
static void
@ -306,7 +304,7 @@ static void pci_testdev_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_testdev_init;
k->realize = pci_testdev_realize;
k->exit = pci_testdev_uninit;
k->vendor_id = PCI_VENDOR_ID_REDHAT;
k->device_id = PCI_DEVICE_ID_REDHAT_TEST;

6
hw/net/e1000.c
View File

@ -1537,7 +1537,7 @@ static void e1000_write_config(PCIDevice *pci_dev, uint32_t address,
}
static int pci_e1000_init(PCIDevice *pci_dev)
static void pci_e1000_realize(PCIDevice *pci_dev, Error **errp)
{
DeviceState *dev = DEVICE(pci_dev);
E1000State *d = E1000(pci_dev);
@ -1581,8 +1581,6 @@ static int pci_e1000_init(PCIDevice *pci_dev)
d->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, e1000_autoneg_timer, d);
d->mit_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000_mit_timer, d);
return 0;
}
static void qdev_e1000_reset(DeviceState *dev)
@ -1614,7 +1612,7 @@ static void e1000_class_init(ObjectClass *klass, void *data)
E1000BaseClass *e = E1000_DEVICE_CLASS(klass);
const E1000Info *info = data;
k->init = pci_e1000_init;
k->realize = pci_e1000_realize;
k->exit = pci_e1000_uninit;
k->romfile = "efi-e1000.rom";
k->vendor_id = PCI_VENDOR_ID_INTEL;

6
hw/net/eepro100.c
View File

@ -1848,7 +1848,7 @@ static NetClientInfo net_eepro100_info = {
.receive = nic_receive,
};
static int e100_nic_init(PCIDevice *pci_dev)
static void e100_nic_realize(PCIDevice *pci_dev, Error **errp)
{
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
E100PCIDeviceInfo *info = eepro100_get_class(s);
@ -1892,8 +1892,6 @@ static int e100_nic_init(PCIDevice *pci_dev)
memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
s->vmstate->name = qemu_get_queue(s->nic)->model;
vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
return 0;
}
static void eepro100_instance_init(Object *obj)
@ -2083,7 +2081,7 @@ static void eepro100_class_init(ObjectClass *klass, void *data)
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->class_id = PCI_CLASS_NETWORK_ETHERNET;
k->romfile = "pxe-eepro100.rom";
k->init = e100_nic_init;
k->realize = e100_nic_realize;
k->exit = pci_nic_uninit;
k->device_id = info->device_id;
k->revision = info->revision;

3
hw/net/lance.c
View File

@ -126,7 +126,8 @@ static int lance_init(SysBusDevice *sbd)
s->phys_mem_read = ledma_memory_read;
s->phys_mem_write = ledma_memory_write;
return pcnet_common_init(dev, s, &net_lance_info);
pcnet_common_init(dev, s, &net_lance_info);
return 0;
}
static void lance_reset(DeviceState *dev)

6
hw/net/ne2000.c
View File

@ -709,7 +709,7 @@ static NetClientInfo net_ne2000_info = {
.receive = ne2000_receive,
};
static int pci_ne2000_init(PCIDevice *pci_dev)
static void pci_ne2000_realize(PCIDevice *pci_dev, Error **errp)
{
PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
NE2000State *s;
@ -729,8 +729,6 @@ static int pci_ne2000_init(PCIDevice *pci_dev)
s->nic = qemu_new_nic(&net_ne2000_info, &s->c,
object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->c.macaddr.a);
return 0;
}
static void pci_ne2000_exit(PCIDevice *pci_dev)
@ -763,7 +761,7 @@ static void ne2000_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_ne2000_init;
k->realize = pci_ne2000_realize;
k->exit = pci_ne2000_exit;
k->romfile = "efi-ne2k_pci.rom",
k->vendor_id = PCI_VENDOR_ID_REALTEK;

6
hw/net/pcnet-pci.c
View File

@ -278,7 +278,7 @@ static NetClientInfo net_pci_pcnet_info = {
.link_status_changed = pcnet_set_link_status,
};
static int pci_pcnet_init(PCIDevice *pci_dev)
static void pci_pcnet_realize(PCIDevice *pci_dev, Error **errp)
{
PCIPCNetState *d = PCI_PCNET(pci_dev);
PCNetState *s = &d->state;
@ -316,7 +316,7 @@ static int pci_pcnet_init(PCIDevice *pci_dev)
s->phys_mem_write = pci_physical_memory_write;
s->dma_opaque = pci_dev;
return pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info);
pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info);
}
static void pci_reset(DeviceState *dev)
@ -346,7 +346,7 @@ static void pcnet_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_pcnet_init;
k->realize = pci_pcnet_realize;
k->exit = pci_pcnet_uninit;
k->romfile = "efi-pcnet.rom",
k->vendor_id = PCI_VENDOR_ID_AMD;

4
hw/net/pcnet.c
View File

@ -1712,7 +1712,7 @@ const VMStateDescription vmstate_pcnet = {
}
};
int pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info)
void pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info)
{
int i;
uint16_t checksum;
@ -1751,6 +1751,4 @@ int pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info)
*(uint16_t *)&s->prom[12] = cpu_to_le16(checksum);
s->lnkst = 0x40; /* initial link state: up */
return 0;
}

2
hw/net/pcnet.h
View File

@ -63,6 +63,6 @@ uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap);
int pcnet_can_receive(NetClientState *nc);
ssize_t pcnet_receive(NetClientState *nc, const uint8_t *buf, size_t size_);
void pcnet_set_link_status(NetClientState *nc);
int pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info);
void pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info);
extern const VMStateDescription vmstate_pcnet;
#endif

6
hw/net/rtl8139.c
View File

@ -3455,7 +3455,7 @@ static NetClientInfo net_rtl8139_info = {
.link_status_changed = rtl8139_set_link_status,
};
static int pci_rtl8139_init(PCIDevice *dev)
static void pci_rtl8139_realize(PCIDevice *dev, Error **errp)
{
RTL8139State *s = RTL8139(dev);
DeviceState *d = DEVICE(dev);
@ -3496,8 +3496,6 @@ static int pci_rtl8139_init(PCIDevice *dev)
s->cplus_txbuffer_offset = 0;
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s);
return 0;
}
static void rtl8139_instance_init(Object *obj)
@ -3519,7 +3517,7 @@ static void rtl8139_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_rtl8139_init;
k->realize = pci_rtl8139_realize;
k->exit = pci_rtl8139_uninit;
k->romfile = "efi-rtl8139.rom";
k->vendor_id = PCI_VENDOR_ID_REALTEK;

2
hw/net/vhost_net.c
View File

@ -35,7 +35,7 @@
#include <stdio.h>
#include "hw/virtio/virtio_ring.h"
#include "standard-headers/linux/virtio_ring.h"
#include "hw/virtio/vhost.h"
#include "hw/virtio/virtio-bus.h"

57
hw/net/virtio-net.c
View File

@ -86,7 +86,7 @@ static void virtio_net_set_config(VirtIODevice *vdev, const uint8_t *config)
memcpy(&netcfg, config, n->config_size);
if (!(vdev->guest_features >> VIRTIO_NET_F_CTRL_MAC_ADDR & 1) &&
if (!virtio_has_feature(vdev, VIRTIO_NET_F_CTRL_MAC_ADDR) &&
memcmp(netcfg.mac, n->mac, ETH_ALEN)) {
memcpy(n->mac, netcfg.mac, ETH_ALEN);
qemu_format_nic_info_str(qemu_get_queue(n->nic), n->mac);
@ -305,7 +305,7 @@ static RxFilterInfo *virtio_net_query_rxfilter(NetClientState *nc)
info->multicast_table = str_list;
info->vlan_table = get_vlan_table(n);
if (!((1 << VIRTIO_NET_F_CTRL_VLAN) & vdev->guest_features)) {
if (!virtio_has_feature(vdev, VIRTIO_NET_F_CTRL_VLAN)) {
info->vlan = RX_STATE_ALL;
} else if (!info->vlan_table) {
info->vlan = RX_STATE_NONE;
@ -446,23 +446,23 @@ static uint32_t virtio_net_get_features(VirtIODevice *vdev, uint32_t features)
VirtIONet *n = VIRTIO_NET(vdev);
NetClientState *nc = qemu_get_queue(n->nic);
features |= (1 << VIRTIO_NET_F_MAC);
virtio_add_feature(&features, VIRTIO_NET_F_MAC);
if (!peer_has_vnet_hdr(n)) {
features &= ~(0x1 << VIRTIO_NET_F_CSUM);
features &= ~(0x1 << VIRTIO_NET_F_HOST_TSO4);
features &= ~(0x1 << VIRTIO_NET_F_HOST_TSO6);
features &= ~(0x1 << VIRTIO_NET_F_HOST_ECN);
virtio_clear_feature(&features, VIRTIO_NET_F_CSUM);
virtio_clear_feature(&features, VIRTIO_NET_F_HOST_TSO4);
virtio_clear_feature(&features, VIRTIO_NET_F_HOST_TSO6);
virtio_clear_feature(&features, VIRTIO_NET_F_HOST_ECN);
features &= ~(0x1 << VIRTIO_NET_F_GUEST_CSUM);
features &= ~(0x1 << VIRTIO_NET_F_GUEST_TSO4);
features &= ~(0x1 << VIRTIO_NET_F_GUEST_TSO6);
features &= ~(0x1 << VIRTIO_NET_F_GUEST_ECN);
virtio_clear_feature(&features, VIRTIO_NET_F_GUEST_CSUM);
virtio_clear_feature(&features, VIRTIO_NET_F_GUEST_TSO4);
virtio_clear_feature(&features, VIRTIO_NET_F_GUEST_TSO6);
virtio_clear_feature(&features, VIRTIO_NET_F_GUEST_ECN);
}
if (!peer_has_vnet_hdr(n) || !peer_has_ufo(n)) {
features &= ~(0x1 << VIRTIO_NET_F_GUEST_UFO);
features &= ~(0x1 << VIRTIO_NET_F_HOST_UFO);
virtio_clear_feature(&features, VIRTIO_NET_F_GUEST_UFO);
virtio_clear_feature(&features, VIRTIO_NET_F_HOST_UFO);
}
if (!get_vhost_net(nc->peer)) {
@ -477,11 +477,11 @@ static uint32_t virtio_net_bad_features(VirtIODevice *vdev)
/* Linux kernel 2.6.25. It understood MAC (as everyone must),
* but also these: */
features |= (1 << VIRTIO_NET_F_MAC);
features |= (1 << VIRTIO_NET_F_CSUM);
features |= (1 << VIRTIO_NET_F_HOST_TSO4);
features |= (1 << VIRTIO_NET_F_HOST_TSO6);
features |= (1 << VIRTIO_NET_F_HOST_ECN);
virtio_add_feature(&features, VIRTIO_NET_F_MAC);
virtio_add_feature(&features, VIRTIO_NET_F_CSUM);
virtio_add_feature(&features, VIRTIO_NET_F_HOST_TSO4);
virtio_add_feature(&features, VIRTIO_NET_F_HOST_TSO6);
virtio_add_feature(&features, VIRTIO_NET_F_HOST_ECN);
return features;
}
@ -519,9 +519,12 @@ static void virtio_net_set_features(VirtIODevice *vdev, uint32_t features)
VirtIONet *n = VIRTIO_NET(vdev);
int i;
virtio_net_set_multiqueue(n, !!(features & (1 << VIRTIO_NET_F_MQ)));
virtio_net_set_multiqueue(n,
__virtio_has_feature(features, VIRTIO_NET_F_MQ));
virtio_net_set_mrg_rx_bufs(n, !!(features & (1 << VIRTIO_NET_F_MRG_RXBUF)));
virtio_net_set_mrg_rx_bufs(n,
__virtio_has_feature(features,
VIRTIO_NET_F_MRG_RXBUF));
if (n->has_vnet_hdr) {
n->curr_guest_offloads =
@ -538,7 +541,7 @@ static void virtio_net_set_features(VirtIODevice *vdev, uint32_t features)
vhost_net_ack_features(get_vhost_net(nc->peer), features);
}
if ((1 << VIRTIO_NET_F_CTRL_VLAN) & features) {
if (__virtio_has_feature(features, VIRTIO_NET_F_CTRL_VLAN)) {
memset(n->vlans, 0, MAX_VLAN >> 3);
} else {
memset(n->vlans, 0xff, MAX_VLAN >> 3);
@ -585,7 +588,7 @@ static int virtio_net_handle_offloads(VirtIONet *n, uint8_t cmd,
uint64_t offloads;
size_t s;
if (!((1 << VIRTIO_NET_F_CTRL_GUEST_OFFLOADS) & vdev->guest_features)) {
if (!virtio_has_feature(vdev, VIRTIO_NET_F_CTRL_GUEST_OFFLOADS)) {
return VIRTIO_NET_ERR;
}
@ -1378,7 +1381,7 @@ static void virtio_net_save_device(VirtIODevice *vdev, QEMUFile *f)
}
}
if ((1 << VIRTIO_NET_F_CTRL_GUEST_OFFLOADS) & vdev->guest_features) {
if (virtio_has_feature(vdev, VIRTIO_NET_F_CTRL_GUEST_OFFLOADS)) {
qemu_put_be64(f, n->curr_guest_offloads);
}
}
@ -1486,7 +1489,7 @@ static int virtio_net_load_device(VirtIODevice *vdev, QEMUFile *f,
}
}
if ((1 << VIRTIO_NET_F_CTRL_GUEST_OFFLOADS) & vdev->guest_features) {
if (virtio_has_feature(vdev, VIRTIO_NET_F_CTRL_GUEST_OFFLOADS)) {
n->curr_guest_offloads = qemu_get_be64(f);
} else {
n->curr_guest_offloads = virtio_net_supported_guest_offloads(n);
@ -1513,8 +1516,8 @@ static int virtio_net_load_device(VirtIODevice *vdev, QEMUFile *f,
qemu_get_subqueue(n->nic, i)->link_down = link_down;
}
if (vdev->guest_features & (0x1 << VIRTIO_NET_F_GUEST_ANNOUNCE) &&
vdev->guest_features & (0x1 << VIRTIO_NET_F_CTRL_VQ)) {
if (virtio_has_feature(vdev, VIRTIO_NET_F_GUEST_ANNOUNCE) &&
virtio_has_feature(vdev, VIRTIO_NET_F_CTRL_VQ)) {
n->announce_counter = SELF_ANNOUNCE_ROUNDS;
timer_mod(n->announce_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL));
}
@ -1552,7 +1555,7 @@ static void virtio_net_guest_notifier_mask(VirtIODevice *vdev, int idx,
void virtio_net_set_config_size(VirtIONet *n, uint32_t host_features)
{
int i, config_size = 0;
host_features |= (1 << VIRTIO_NET_F_MAC);
virtio_add_feature(&host_features, VIRTIO_NET_F_MAC);
for (i = 0; feature_sizes[i].flags != 0; i++) {
if (host_features & feature_sizes[i].flags) {
config_size = MAX(feature_sizes[i].end, config_size);

6
hw/net/vmxnet3.c
View File

@ -2125,7 +2125,7 @@ static const MemoryRegionOps b1_ops = {
},
};
static int vmxnet3_pci_init(PCIDevice *pci_dev)
static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
{
DeviceState *dev = DEVICE(pci_dev);
VMXNET3State *s = VMXNET3(pci_dev);
@ -2164,8 +2164,6 @@ static int vmxnet3_pci_init(PCIDevice *pci_dev)
register_savevm(dev, "vmxnet3-msix", -1, 1,
vmxnet3_msix_save, vmxnet3_msix_load, s);
return 0;
}
static void vmxnet3_instance_init(Object *obj)
@ -2501,7 +2499,7 @@ static void vmxnet3_class_init(ObjectClass *class, void *data)
DeviceClass *dc = DEVICE_CLASS(class);
PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
c->init = vmxnet3_pci_init;
c->realize = vmxnet3_pci_realize;
c->exit = vmxnet3_pci_uninit;
c->vendor_id = PCI_VENDOR_ID_VMWARE;
c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;

5
hw/pci-bridge/dec.c
View File

@ -107,10 +107,9 @@ static int pci_dec_21154_device_init(SysBusDevice *dev)
return 0;
}
static int dec_21154_pci_host_init(PCIDevice *d)
static void dec_21154_pci_host_realize(PCIDevice *d, Error **errp)
{
/* PCI2PCI bridge same values as PearPC - check this */
return 0;
}
static void dec_21154_pci_host_class_init(ObjectClass *klass, void *data)
@ -118,7 +117,7 @@ static void dec_21154_pci_host_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = dec_21154_pci_host_init;
k->realize = dec_21154_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_DEC;
k->device_id = PCI_DEVICE_ID_DEC_21154;
k->revision = 0x02;

5
hw/pci-host/apb.c
View File

@ -792,14 +792,13 @@ static int pci_pbm_init_device(SysBusDevice *dev)
return 0;
}
static int pbm_pci_host_init(PCIDevice *d)
static void pbm_pci_host_realize(PCIDevice *d, Error **errp)
{
pci_set_word(d->config + PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
pci_set_word(d->config + PCI_STATUS,
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
PCI_STATUS_DEVSEL_MEDIUM);
return 0;
}
static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
@ -807,7 +806,7 @@ static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = pbm_pci_host_init;
k->realize = pbm_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_SUN;
k->device_id = PCI_DEVICE_ID_SUN_SABRE;
k->class_id = PCI_CLASS_BRIDGE_HOST;

6
hw/pci-host/bonito.c
View File

@ -705,7 +705,7 @@ static int bonito_pcihost_initfn(SysBusDevice *dev)
return 0;
}
static int bonito_initfn(PCIDevice *dev)
static void bonito_realize(PCIDevice *dev, Error **errp)
{
PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev);
SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost);
@ -766,8 +766,6 @@ static int bonito_initfn(PCIDevice *dev)
pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
qemu_register_reset(bonito_reset, s);
return 0;
}
PCIBus *bonito_init(qemu_irq *pic)
@ -799,7 +797,7 @@ static void bonito_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = bonito_initfn;
k->realize = bonito_realize;
k->vendor_id = 0xdf53;
k->device_id = 0x00d5;
k->revision = 0x01;

5
hw/pci-host/grackle.c
View File

@ -114,10 +114,9 @@ static int pci_grackle_init_device(SysBusDevice *dev)
return 0;
}
static int grackle_pci_host_init(PCIDevice *d)
static void grackle_pci_host_realize(PCIDevice *d, Error **errp)
{
d->config[0x09] = 0x01;
return 0;
}
static void grackle_pci_class_init(ObjectClass *klass, void *data)
@ -125,7 +124,7 @@ static void grackle_pci_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = grackle_pci_host_init;
k->realize = grackle_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
k->device_id = PCI_DEVICE_ID_MOTOROLA_MPC106;
k->revision = 0x00;

12
hw/pci-host/piix.c
View File

@ -295,14 +295,13 @@ static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
sysbus_init_ioports(sbd, 0xcfc, 4);
}
static int i440fx_initfn(PCIDevice *dev)
static void i440fx_realize(PCIDevice *dev, Error **errp)
{
PCII440FXState *d = I440FX_PCI_DEVICE(dev);
dev->config[I440FX_SMRAM] = 0x02;
cpu_smm_register(&i440fx_set_smm, d);
return 0;
}
PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
@ -631,7 +630,7 @@ static const MemoryRegionOps rcr_ops = {
.endianness = DEVICE_LITTLE_ENDIAN
};
static int piix3_initfn(PCIDevice *dev)
static void piix3_realize(PCIDevice *dev, Error **errp)
{
PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
@ -644,7 +643,6 @@ static int piix3_initfn(PCIDevice *dev)
&d->rcr_mem, 1);
qemu_register_reset(piix3_reset, d);
return 0;
}
static void piix3_class_init(ObjectClass *klass, void *data)
@ -655,7 +653,7 @@ static void piix3_class_init(ObjectClass *klass, void *data)
dc->desc = "ISA bridge";
dc->vmsd = &vmstate_piix3;
dc->hotpluggable = false;
k->init = piix3_initfn;
k->realize = piix3_realize;
k->config_write = piix3_write_config;
k->vendor_id = PCI_VENDOR_ID_INTEL;
/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
@ -683,7 +681,7 @@ static void piix3_xen_class_init(ObjectClass *klass, void *data)
dc->desc = "ISA bridge";
dc->vmsd = &vmstate_piix3;
dc->hotpluggable = false;
k->init = piix3_initfn;
k->realize = piix3_realize;
k->config_write = piix3_write_config_xen;
k->vendor_id = PCI_VENDOR_ID_INTEL;
/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
@ -708,7 +706,7 @@ static void i440fx_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = i440fx_initfn;
k->realize = i440fx_realize;
k->config_write = i440fx_write_config;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82441;

6
hw/pci-host/ppce500.c
View File

@ -416,7 +416,7 @@ static const VMStateDescription vmstate_ppce500_pci = {
#include "exec/address-spaces.h"
static int e500_pcihost_bridge_initfn(PCIDevice *d)
static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp)
{
PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
@ -430,8 +430,6 @@ static int e500_pcihost_bridge_initfn(PCIDevice *d)
memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space,
0, int128_get64(ccsr->ccsr_space.size));
pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
return 0;
}
static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque,
@ -500,7 +498,7 @@ static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = e500_pcihost_bridge_initfn;
k->realize = e500_pcihost_bridge_realize;
k->vendor_id = PCI_VENDOR_ID_FREESCALE;
k->device_id = PCI_DEVICE_ID_MPC8533E;
k->class_id = PCI_CLASS_PROCESSOR_POWERPC;

6
hw/pci-host/prep.c
View File

@ -289,7 +289,7 @@ static void raven_pcihost_initfn(Object *obj)
qdev_prop_set_bit(pci_dev, "multifunction", false);
}
static int raven_init(PCIDevice *d)
static void raven_realize(PCIDevice *d, Error **errp)
{
RavenPCIState *s = RAVEN_PCI_DEVICE(d);
char *filename;
@ -330,8 +330,6 @@ static int raven_init(PCIDevice *d)
g_free(filename);
}
}
return 0;
}
static const VMStateDescription vmstate_raven = {
@ -349,7 +347,7 @@ static void raven_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = raven_init;
k->realize = raven_realize;
k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
k->revision = 0x00;

5
hw/pci-host/q35.c
View File

@ -390,7 +390,7 @@ static void mch_init_dmar(MCHPCIState *mch)
pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu);
}
static int mch_init(PCIDevice *d)
static void mch_realize(PCIDevice *d, Error **errp)
{
int i;
MCHPCIState *mch = MCH_PCI_DEVICE(d);
@ -418,7 +418,6 @@ static int mch_init(PCIDevice *d)
if (qemu_opt_get_bool(qemu_get_machine_opts(), "iommu", false)) {
mch_init_dmar(mch);
}
return 0;
}
uint64_t mch_mcfg_base(void)
@ -436,7 +435,7 @@ static void mch_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = mch_init;
k->realize = mch_realize;
k->config_write = mch_write_config;
dc->reset = mch_reset;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);

20
hw/pci-host/uninorth.c
View File

@ -315,37 +315,33 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
return h->bus;
}
static int unin_main_pci_host_init(PCIDevice *d)
static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
{
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
d->config[0x34] = 0x00; // capabilities_pointer
return 0;
}
static int unin_agp_pci_host_init(PCIDevice *d)
static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
// d->config[0x34] = 0x80; // capabilities_pointer
return 0;
}
static int u3_agp_pci_host_init(PCIDevice *d)
static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
/* cache line size */
d->config[0x0C] = 0x08;
/* latency timer */
d->config[0x0D] = 0x10;
return 0;
}
static int unin_internal_pci_host_init(PCIDevice *d)
static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
{
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
d->config[0x34] = 0x00; // capabilities_pointer
return 0;
}
static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
@ -353,7 +349,7 @@ static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = unin_main_pci_host_init;
k->realize = unin_main_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_APPLE;
k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
k->revision = 0x00;
@ -377,7 +373,7 @@ static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = u3_agp_pci_host_init;
k->realize = u3_agp_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_APPLE;
k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
k->revision = 0x00;
@ -401,7 +397,7 @@ static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = unin_agp_pci_host_init;
k->realize = unin_agp_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_APPLE;
k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
k->revision = 0x00;
@ -425,7 +421,7 @@ static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = unin_internal_pci_host_init;
k->realize = unin_internal_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_APPLE;
k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
k->revision = 0x00;

5
hw/pci-host/versatile.c
View File

@ -456,12 +456,11 @@ static void pci_vpb_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
}
static int versatile_pci_host_init(PCIDevice *d)
static void versatile_pci_host_realize(PCIDevice *d, Error **errp)
{
pci_set_word(d->config + PCI_STATUS,
PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
return 0;
}
static void versatile_pci_host_class_init(ObjectClass *klass, void *data)
@ -469,7 +468,7 @@ static void versatile_pci_host_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = versatile_pci_host_init;
k->realize = versatile_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_XILINX;
k->device_id = PCI_DEVICE_ID_XILINX_XC2VP30;
k->class_id = PCI_CLASS_PROCESSOR_CO;

2
hw/pci/Makefile.objs
View File

@ -7,5 +7,3 @@ common-obj-$(CONFIG_PCI) += pcie.o pcie_aer.o pcie_port.o
common-obj-$(call lnot,$(CONFIG_PCI)) += pci-stub.o
common-obj-$(CONFIG_ALL) += pci-stub.o
common-obj-$(CONFIG_PCI_HOTPLUG_OLD) += pci-hotplug-old.o

342
hw/pci/pci-hotplug-old.c
View File

@ -1,342 +0,0 @@
/*
* Deprecated PCI hotplug interface support
* This covers the old pci_add / pci_del command, whereas the more general
* device_add / device_del commands are now preferred.
*
* Copyright (c) 2004 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "hw/hw.h"
#include "hw/boards.h"
#include "hw/pci/pci.h"
#include "net/net.h"
#include "hw/i386/pc.h"
#include "monitor/monitor.h"
#include "hw/scsi/scsi.h"
#include "hw/virtio/virtio-blk.h"
#include "qemu/config-file.h"
#include "sysemu/block-backend.h"
#include "qapi/error.h"
static int pci_read_devaddr(Monitor *mon, const char *addr,
int *busp, unsigned *slotp)
{
int dom;
/* strip legacy tag */
if (!strncmp(addr, "pci_addr=", 9)) {
addr += 9;
}
if (pci_parse_devaddr(addr, &dom, busp, slotp, NULL)) {
monitor_printf(mon, "Invalid pci address\n");
return -1;
}
if (dom != 0) {
monitor_printf(mon, "Multiple PCI domains not supported, use device_add\n");
return -1;
}
return 0;
}
static PCIDevice *qemu_pci_hot_add_nic(Monitor *mon,
const char *devaddr,
const char *opts_str)
{
Error *local_err = NULL;
QemuOpts *opts;
PCIBus *root = pci_find_primary_bus();
PCIBus *bus;
int ret, devfn;
if (!root) {
monitor_printf(mon, "no primary PCI bus (if there are multiple"
" PCI roots, you must use device_add instead)");
return NULL;
}
bus = pci_get_bus_devfn(&devfn, root, devaddr);
if (!bus) {
monitor_printf(mon, "Invalid PCI device address %s\n", devaddr);
return NULL;
}
if (!qbus_is_hotpluggable(BUS(bus))) {
monitor_printf(mon, "PCI bus doesn't support hotplug\n");
return NULL;
}
opts = qemu_opts_parse(qemu_find_opts("net"), opts_str ? opts_str : "", 0);
if (!opts) {
return NULL;
}
qemu_opt_set(opts, "type", "nic", &error_abort);
ret = net_client_init(opts, 0, &local_err);
if (local_err) {
qerror_report_err(local_err);
error_free(local_err);
return NULL;
}
if (nd_table[ret].devaddr) {
monitor_printf(mon, "Parameter addr not supported\n");
return NULL;
}
return pci_nic_init(&nd_table[ret], root, "rtl8139", devaddr);
}
static int scsi_hot_add(Monitor *mon, DeviceState *adapter,
DriveInfo *dinfo, int printinfo)
{
SCSIBus *scsibus;
SCSIDevice *scsidev;
Error *local_err = NULL;
scsibus = (SCSIBus *)
object_dynamic_cast(OBJECT(QLIST_FIRST(&adapter->child_bus)),
TYPE_SCSI_BUS);
if (!scsibus) {
error_report("Device is not a SCSI adapter");
return -1;
}
/*
* drive_init() tries to find a default for dinfo->unit. Doesn't
* work at all for hotplug though as we assign the device to a
* specific bus instead of the first bus with spare scsi ids.
*
* Ditch the calculated value and reload from option string (if
* specified).
*/
dinfo->unit = qemu_opt_get_number(dinfo->opts, "unit", -1);
dinfo->bus = scsibus->busnr;
scsidev = scsi_bus_legacy_add_drive(scsibus,
blk_by_legacy_dinfo(dinfo),
dinfo->unit, false, -1, NULL,
&local_err);
if (!scsidev) {
error_report_err(local_err);
return -1;
}
dinfo->unit = scsidev->id;
if (printinfo)
monitor_printf(mon, "OK bus %d, unit %d\n",
scsibus->busnr, scsidev->id);
return 0;
}
int pci_drive_hot_add(Monitor *mon, const QDict *qdict, DriveInfo *dinfo)
{
int pci_bus;
unsigned slot;
PCIBus *root = pci_find_primary_bus();
PCIDevice *dev;
const char *pci_addr = qdict_get_str(qdict, "pci_addr");
switch (dinfo->type) {
case IF_SCSI:
if (!root) {
monitor_printf(mon, "no primary PCI bus (if there are multiple"
" PCI roots, you must use device_add instead)");
goto err;
}
if (pci_read_devaddr(mon, pci_addr, &pci_bus, &slot)) {
goto err;
}
dev = pci_find_device(root, pci_bus, PCI_DEVFN(slot, 0));
if (!dev) {
monitor_printf(mon, "no pci device with address %s\n", pci_addr);
goto err;
}
if (scsi_hot_add(mon, &dev->qdev, dinfo, 1) != 0) {
goto err;
}
break;
default:
monitor_printf(mon, "Can't hot-add drive to type %d\n", dinfo->type);
goto err;
}
return 0;
err:
return -1;
}
static PCIDevice *qemu_pci_hot_add_storage(Monitor *mon,
const char *devaddr,
const char *opts)
{
PCIDevice *dev;
DriveInfo *dinfo = NULL;
int type = -1;
char buf[128];
PCIBus *root = pci_find_primary_bus();
PCIBus *bus;
int devfn;
if (get_param_value(buf, sizeof(buf), "if", opts)) {
if (!strcmp(buf, "scsi"))
type = IF_SCSI;
else if (!strcmp(buf, "virtio")) {
type = IF_VIRTIO;
} else {
monitor_printf(mon, "type %s not a hotpluggable PCI device.\n", buf);
return NULL;
}
} else {
monitor_printf(mon, "no if= specified\n");
return NULL;
}
if (get_param_value(buf, sizeof(buf), "file", opts)) {
dinfo = add_init_drive(opts);
if (!dinfo)
return NULL;
if (dinfo->devaddr) {
monitor_printf(mon, "Parameter addr not supported\n");
return NULL;
}
} else {
dinfo = NULL;
}
if (!root) {
monitor_printf(mon, "no primary PCI bus (if there are multiple"
" PCI roots, you must use device_add instead)");
return NULL;
}
bus = pci_get_bus_devfn(&devfn, root, devaddr);
if (!bus) {
monitor_printf(mon, "Invalid PCI device address %s\n", devaddr);
return NULL;
}
if (!qbus_is_hotpluggable(BUS(bus))) {
monitor_printf(mon, "PCI bus doesn't support hotplug\n");
return NULL;
}
switch (type) {
case IF_SCSI:
dev = pci_create(bus, devfn, "lsi53c895a");
if (qdev_init(&dev->qdev) < 0)
dev = NULL;
if (dev && dinfo) {
if (scsi_hot_add(mon, &dev->qdev, dinfo, 0) != 0) {
qdev_unplug(&dev->qdev, NULL);
dev = NULL;
}
}
break;
case IF_VIRTIO:
if (!dinfo) {
monitor_printf(mon, "virtio requires a backing file/device.\n");
return NULL;
}
dev = pci_create(bus, devfn, "virtio-blk-pci");
if (qdev_prop_set_drive(&dev->qdev, "drive",
blk_by_legacy_dinfo(dinfo)) < 0) {
object_unparent(OBJECT(dev));
dev = NULL;
break;
}
if (qdev_init(&dev->qdev) < 0)
dev = NULL;
break;
default:
dev = NULL;
}
return dev;
}
void hmp_pci_add(Monitor *mon, const QDict *qdict)
{
PCIDevice *dev = NULL;
const char *pci_addr = qdict_get_str(qdict, "pci_addr");
const char *type = qdict_get_str(qdict, "type");
const char *opts = qdict_get_try_str(qdict, "opts");
/* strip legacy tag */
if (!strncmp(pci_addr, "pci_addr=", 9)) {
pci_addr += 9;
}
if (!opts) {
opts = "";
}
if (!strcmp(pci_addr, "auto"))
pci_addr = NULL;
if (strcmp(type, "nic") == 0) {
dev = qemu_pci_hot_add_nic(mon, pci_addr, opts);
} else if (strcmp(type, "storage") == 0) {
dev = qemu_pci_hot_add_storage(mon, pci_addr, opts);
} else {
monitor_printf(mon, "invalid type: %s\n", type);
}
if (dev) {
monitor_printf(mon, "OK root bus %s, bus %d, slot %d, function %d\n",
pci_root_bus_path(dev),
pci_bus_num(dev->bus), PCI_SLOT(dev->devfn),
PCI_FUNC(dev->devfn));
} else
monitor_printf(mon, "failed to add %s\n", opts);
}
static int pci_device_hot_remove(Monitor *mon, const char *pci_addr)
{
PCIBus *root = pci_find_primary_bus();
PCIDevice *d;
int bus;
unsigned slot;
Error *local_err = NULL;
if (!root) {
monitor_printf(mon, "no primary PCI bus (if there are multiple"
" PCI roots, you must use device_del instead)");
return -1;
}
if (pci_read_devaddr(mon, pci_addr, &bus, &slot)) {
return -1;
}
d = pci_find_device(root, bus, PCI_DEVFN(slot, 0));
if (!d) {
monitor_printf(mon, "slot %d empty\n", slot);
return -1;
}
qdev_unplug(&d->qdev, &local_err);
if (local_err) {
monitor_printf(mon, "%s\n", error_get_pretty(local_err));
error_free(local_err);
return -1;
}
return 0;
}
void hmp_pci_del(Monitor *mon, const QDict *qdict)
{
pci_device_hot_remove(mon, qdict_get_str(qdict, "pci_addr"));
}

127
hw/pci/pci.c
View File

@ -115,7 +115,7 @@ static const TypeInfo pcie_bus_info = {
static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
static void pci_update_mappings(PCIDevice *d);
static void pci_irq_handler(void *opaque, int irq_num, int level);
static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
static void pci_del_option_rom(PCIDevice *pdev);
static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
@ -539,8 +539,8 @@ static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
* Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
* [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
*/
int pci_parse_devaddr(const char *addr, int *domp, int *busp,
unsigned int *slotp, unsigned int *funcp)
static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
unsigned int *slotp, unsigned int *funcp)
{
const char *p;
char *e;
@ -598,7 +598,8 @@ int pci_parse_devaddr(const char *addr, int *domp, int *busp,
return 0;
}
PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr)
static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root,
const char *devaddr)
{
int dom, bus;
unsigned slot;
@ -726,7 +727,7 @@ static void pci_init_mask_bridge(PCIDevice *d)
PCI_PREF_RANGE_TYPE_MASK);
}
static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
{
uint8_t slot = PCI_SLOT(dev->devfn);
uint8_t func;
@ -752,26 +753,25 @@ static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
/* function 0 should set multifunction bit */
error_report("PCI: single function device can't be populated "
"in function %x.%x", slot, PCI_FUNC(dev->devfn));
return -1;
error_setg(errp, "PCI: single function device can't be populated "
"in function %x.%x", slot, PCI_FUNC(dev->devfn));
return;
}
return 0;
return;
}
if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
return 0;
return;
}
/* function 0 indicates single function, so function > 0 must be NULL */
for (func = 1; func < PCI_FUNC_MAX; ++func) {
if (bus->devices[PCI_DEVFN(slot, func)]) {
error_report("PCI: %x.0 indicates single function, "
"but %x.%x is already populated.",
slot, slot, func);
return -1;
error_setg(errp, "PCI: %x.0 indicates single function, "
"but %x.%x is already populated.",
slot, slot, func);
return;
}
}
return 0;
}
static void pci_config_alloc(PCIDevice *pci_dev)
@ -804,11 +804,13 @@ static void do_pci_unregister_device(PCIDevice *pci_dev)
/* -1 for devfn means auto assign */
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
const char *name, int devfn)
const char *name, int devfn,
Error **errp)
{
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
PCIConfigReadFunc *config_read = pc->config_read;
PCIConfigWriteFunc *config_write = pc->config_write;
Error *local_err = NULL;
AddressSpace *dma_as;
if (devfn < 0) {
@ -817,12 +819,15 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
if (!bus->devices[devfn])
goto found;
}
error_report("PCI: no slot/function available for %s, all in use", name);
error_setg(errp, "PCI: no slot/function available for %s, all in use",
name);
return NULL;
found: ;
} else if (bus->devices[devfn]) {
error_report("PCI: slot %d function %d not available for %s, in use by %s",
PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
error_setg(errp, "PCI: slot %d function %d not available for %s,"
" in use by %s",
PCI_SLOT(devfn), PCI_FUNC(devfn), name,
bus->devices[devfn]->name);
return NULL;
}
@ -866,7 +871,9 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
if (pc->is_bridge) {
pci_init_mask_bridge(pci_dev);
}
if (pci_init_multifunction(bus, pci_dev)) {
pci_init_multifunction(bus, pci_dev, &local_err);
if (local_err) {
error_propagate(errp, local_err);
do_pci_unregister_device(pci_dev);
return NULL;
}
@ -897,7 +904,7 @@ static void pci_unregister_io_regions(PCIDevice *pci_dev)
pci_unregister_vga(pci_dev);
}
static int pci_unregister_device(DeviceState *dev)
static void pci_qdev_unrealize(DeviceState *dev, Error **errp)
{
PCIDevice *pci_dev = PCI_DEVICE(dev);
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
@ -910,7 +917,6 @@ static int pci_unregister_device(DeviceState *dev)
}
do_pci_unregister_device(pci_dev);
return 0;
}
void pci_register_bar(PCIDevice *pci_dev, int region_num,
@ -1605,10 +1611,9 @@ static const char * const pci_nic_names[] = {
};
/* Initialize a PCI NIC. */
/* FIXME callers should check for failure, but don't */
PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus,
const char *default_model,
const char *default_devaddr)
static PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus,
const char *default_model,
const char *default_devaddr)
{
const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
PCIBus *bus;
@ -1751,12 +1756,12 @@ PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
return bus->devices[devfn];
}
static int pci_qdev_init(DeviceState *qdev)
static void pci_qdev_realize(DeviceState *qdev, Error **errp)
{
PCIDevice *pci_dev = (PCIDevice *)qdev;
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
Error *local_err = NULL;
PCIBus *bus;
int rc;
bool is_default_rom;
/* initialize cap_present for pci_is_express() and pci_config_size() */
@ -1767,15 +1772,16 @@ static int pci_qdev_init(DeviceState *qdev)
bus = PCI_BUS(qdev_get_parent_bus(qdev));
pci_dev = do_pci_register_device(pci_dev, bus,
object_get_typename(OBJECT(qdev)),
pci_dev->devfn);
pci_dev->devfn, errp);
if (pci_dev == NULL)
return -1;
return;
if (pc->init) {
rc = pc->init(pci_dev);
if (rc != 0) {
if (pc->realize) {
pc->realize(pci_dev, &local_err);
if (local_err) {
error_propagate(errp, local_err);
do_pci_unregister_device(pci_dev);
return rc;
return;
}
}
@ -1786,13 +1792,24 @@ static int pci_qdev_init(DeviceState *qdev)
is_default_rom = true;
}
rc = pci_add_option_rom(pci_dev, is_default_rom);
if (rc != 0) {
pci_unregister_device(DEVICE(pci_dev));
return rc;
pci_add_option_rom(pci_dev, is_default_rom, &local_err);
if (local_err) {
error_propagate(errp, local_err);
pci_qdev_unrealize(DEVICE(pci_dev), NULL);
return;
}
}
return 0;
static void pci_default_realize(PCIDevice *dev, Error **errp)
{
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
if (pc->init) {
if (pc->init(dev) < 0) {
error_setg(errp, "Device initialization failed");
return;
}
}
}
PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
@ -1932,7 +1949,8 @@ static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
}
/* Add an option rom for the device */
static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
Error **errp)
{
int size;
char *path;
@ -1941,9 +1959,9 @@ static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
const VMStateDescription *vmsd;
if (!pdev->romfile)
return 0;
return;
if (strlen(pdev->romfile) == 0)
return 0;
return;
if (!pdev->rom_bar) {
/*
@ -1957,7 +1975,9 @@ static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
* if the rom bar is disabled.
*/
if (DEVICE(pdev)->hotplugged) {
return -1;
error_setg(errp, "Hot-plugged device without ROM bar"
" can't have an option ROM");
return;
}
if (class == 0x0300) {
@ -1965,7 +1985,7 @@ static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
} else {
rom_add_option(pdev->romfile, -1);
}
return 0;
return;
}
path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
@ -1975,15 +1995,13 @@ static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
size = get_image_size(path);
if (size < 0) {
error_report("%s: failed to find romfile \"%s\"",
__func__, pdev->romfile);
error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
g_free(path);
return -1;
return;
} else if (size == 0) {
error_report("%s: ignoring empty romfile \"%s\"",
__func__, pdev->romfile);
error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
g_free(path);
return -1;
return;
}
if (size & (size - 1)) {
size = 1 << qemu_fls(size);
@ -2009,8 +2027,6 @@ static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
}
pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
return 0;
}
static void pci_del_option_rom(PCIDevice *pdev)
@ -2291,10 +2307,13 @@ MemoryRegion *pci_address_space_io(PCIDevice *dev)
static void pci_device_class_init(ObjectClass *klass, void *data)
{
DeviceClass *k = DEVICE_CLASS(klass);
k->init = pci_qdev_init;
k->exit = pci_unregister_device;
PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
k->realize = pci_qdev_realize;
k->unrealize = pci_qdev_unrealize;
k->bus_type = TYPE_PCI_BUS;
k->props = pci_props;
pc->realize = pci_default_realize;
}
AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)

36
hw/s390x/s390-virtio-bus.h
View File

@ -19,6 +19,10 @@
#ifndef HW_S390_VIRTIO_BUS_H
#define HW_S390_VIRTIO_BUS_H 1
#include <stddef.h>
#include "standard-headers/asm-s390/kvm_virtio.h"
#include "standard-headers/linux/virtio_ring.h"
#include "hw/virtio/virtio-blk.h"
#include "hw/virtio/virtio-net.h"
#include "hw/virtio/virtio-rng.h"
@ -29,28 +33,26 @@
#include "hw/virtio/vhost-scsi.h"
#endif
#define VIRTIO_DEV_OFFS_TYPE 0 /* 8 bits */
#define VIRTIO_DEV_OFFS_NUM_VQ 1 /* 8 bits */
#define VIRTIO_DEV_OFFS_FEATURE_LEN 2 /* 8 bits */
#define VIRTIO_DEV_OFFS_CONFIG_LEN 3 /* 8 bits */
#define VIRTIO_DEV_OFFS_STATUS 4 /* 8 bits */
#define VIRTIO_DEV_OFFS_CONFIG 5 /* dynamic */
typedef struct kvm_device_desc KvmDeviceDesc;
#define VIRTIO_VQCONFIG_OFFS_TOKEN 0 /* 64 bits */
#define VIRTIO_VQCONFIG_OFFS_ADDRESS 8 /* 64 bits */
#define VIRTIO_VQCONFIG_OFFS_NUM 16 /* 16 bits */
#define VIRTIO_VQCONFIG_LEN 24
#define VIRTIO_DEV_OFFS_TYPE offsetof(KvmDeviceDesc, type)
#define VIRTIO_DEV_OFFS_NUM_VQ offsetof(KvmDeviceDesc, num_vq)
#define VIRTIO_DEV_OFFS_FEATURE_LEN offsetof(KvmDeviceDesc, feature_len)
#define VIRTIO_DEV_OFFS_CONFIG_LEN offsetof(KvmDeviceDesc, config_len)
#define VIRTIO_DEV_OFFS_STATUS offsetof(KvmDeviceDesc, status)
#define VIRTIO_DEV_OFFS_CONFIG offsetof(KvmDeviceDesc, config)
typedef struct kvm_vqconfig KvmVqConfig;
#define VIRTIO_VQCONFIG_OFFS_TOKEN offsetof(KvmVqConfig,token) /* 64 bit */
#define VIRTIO_VQCONFIG_OFFS_ADDRESS offsetof(KvmVqConfig, address) /* 64 bit */
#define VIRTIO_VQCONFIG_OFFS_NUM offsetof(KvmVqConfig, num) /* 16 bit */
#define VIRTIO_VQCONFIG_LEN sizeof(KvmVqConfig)
#define VIRTIO_RING_LEN (TARGET_PAGE_SIZE * 3)
#define VIRTIO_VRING_AVAIL_IDX_OFFS 2
#define VIRTIO_VRING_USED_IDX_OFFS 2
#define VIRTIO_VRING_AVAIL_IDX_OFFS offsetof(struct vring_avail, idx)
#define VIRTIO_VRING_USED_IDX_OFFS offsetof(struct vring_used, idx)
#define S390_DEVICE_PAGES 512
#define VIRTIO_PARAM_MASK 0xff
#define VIRTIO_PARAM_VRING_INTERRUPT 0x0
#define VIRTIO_PARAM_CONFIG_CHANGED 0x1
#define VIRTIO_PARAM_DEV_ADD 0x2
#define TYPE_VIRTIO_S390_DEVICE "virtio-s390-device"
#define VIRTIO_S390_DEVICE(obj) \
OBJECT_CHECK(VirtIOS390Device, (obj), TYPE_VIRTIO_S390_DEVICE)

7
hw/s390x/s390-virtio.h
View File

@ -13,11 +13,8 @@
#define HW_S390_VIRTIO_H 1
#include "hw/nmi.h"
#define KVM_S390_VIRTIO_NOTIFY 0
#define KVM_S390_VIRTIO_RESET 1
#define KVM_S390_VIRTIO_SET_STATUS 2
#define KVM_S390_VIRTIO_CCW_NOTIFY 3
#include "standard-headers/asm-s390/kvm_virtio.h"
#include "standard-headers/asm-s390/virtio-ccw.h"
typedef int (*s390_virtio_fn)(const uint64_t *args);
void s390_register_virtio_hypercall(uint64_t code, s390_virtio_fn fn);

12
hw/s390x/virtio-ccw.c
View File

@ -400,8 +400,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
ccw.cda + sizeof(features.features));
features.features = ldl_le_phys(&address_space_memory, ccw.cda);
if (features.index < ARRAY_SIZE(dev->host_features)) {
virtio_bus_set_vdev_features(&dev->bus, features.features);
vdev->guest_features = features.features;
virtio_set_features(vdev, features.features);
} else {
/*
* If the guest supports more feature bits, assert that it
@ -744,8 +743,8 @@ static int virtio_ccw_device_init(VirtioCcwDevice *dev, VirtIODevice *vdev)
dev->host_features[0] = virtio_bus_get_vdev_features(&dev->bus,
dev->host_features[0]);
dev->host_features[0] |= 0x1 << VIRTIO_F_NOTIFY_ON_EMPTY;
dev->host_features[0] |= 0x1 << VIRTIO_F_BAD_FEATURE;
virtio_add_feature(&dev->host_features[0], VIRTIO_F_NOTIFY_ON_EMPTY);
virtio_add_feature(&dev->host_features[0], VIRTIO_F_BAD_FEATURE);
css_generate_sch_crws(sch->cssid, sch->ssid, sch->schid,
parent->hotplugged, 1);
@ -899,9 +898,8 @@ static void balloon_ccw_stats_set_poll_interval(Object *obj, struct Visitor *v,
static void virtio_ccw_balloon_instance_init(Object *obj)
{
VirtIOBalloonCcw *dev = VIRTIO_BALLOON_CCW(obj);
object_initialize(&dev->vdev, sizeof(dev->vdev), TYPE_VIRTIO_BALLOON);
object_property_add_child(obj, "virtio-backend", OBJECT(&dev->vdev), NULL);
object_unref(OBJECT(&dev->vdev));
virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
TYPE_VIRTIO_BALLOON);
object_property_add(obj, "guest-stats", "guest statistics",
balloon_ccw_stats_get_all, NULL, NULL, dev, NULL);

9
hw/scsi/virtio-scsi.c
View File

@ -13,6 +13,7 @@
*
*/
#include "standard-headers/linux/virtio_ids.h"
#include "hw/virtio/virtio-scsi.h"
#include "qemu/error-report.h"
#include "qemu/iov.h"
@ -144,7 +145,7 @@ static int virtio_scsi_parse_req(VirtIOSCSIReq *req,
*
* TODO: always disable this workaround for virtio 1.0 devices.
*/
if ((vdev->guest_features & (1 << VIRTIO_F_ANY_LAYOUT)) == 0) {
if (!virtio_has_feature(vdev, VIRTIO_F_ANY_LAYOUT)) {
req_size = req->elem.out_sg[0].iov_len;
resp_size = req->elem.in_sg[0].iov_len;
}
@ -744,7 +745,7 @@ static void virtio_scsi_change(SCSIBus *bus, SCSIDevice *dev, SCSISense sense)
VirtIOSCSI *s = container_of(bus, VirtIOSCSI, bus);
VirtIODevice *vdev = VIRTIO_DEVICE(s);
if (((vdev->guest_features >> VIRTIO_SCSI_F_CHANGE) & 1) &&
if (virtio_has_feature(vdev, VIRTIO_SCSI_F_CHANGE) &&
dev->type != TYPE_ROM) {
virtio_scsi_push_event(s, dev, VIRTIO_SCSI_T_PARAM_CHANGE,
sense.asc | (sense.ascq << 8));
@ -768,7 +769,7 @@ static void virtio_scsi_hotplug(HotplugHandler *hotplug_dev, DeviceState *dev,
aio_context_release(s->ctx);
}
if ((vdev->guest_features >> VIRTIO_SCSI_F_HOTPLUG) & 1) {
if (virtio_has_feature(vdev, VIRTIO_SCSI_F_HOTPLUG)) {
virtio_scsi_push_event(s, sd,
VIRTIO_SCSI_T_TRANSPORT_RESET,
VIRTIO_SCSI_EVT_RESET_RESCAN);
@ -782,7 +783,7 @@ static void virtio_scsi_hotunplug(HotplugHandler *hotplug_dev, DeviceState *dev,
VirtIOSCSI *s = VIRTIO_SCSI(vdev);
SCSIDevice *sd = SCSI_DEVICE(dev);
if ((vdev->guest_features >> VIRTIO_SCSI_F_HOTPLUG) & 1) {
if (virtio_has_feature(vdev, VIRTIO_SCSI_F_HOTPLUG)) {
virtio_scsi_push_event(s, sd,
VIRTIO_SCSI_T_TRANSPORT_RESET,
VIRTIO_SCSI_EVT_RESET_REMOVED);

5
hw/sd/sdhci.c
View File

@ -1220,7 +1220,7 @@ static Property sdhci_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
static int sdhci_pci_init(PCIDevice *dev)
static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
{
SDHCIState *s = PCI_SDHCI(dev);
dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */
@ -1232,7 +1232,6 @@ static int sdhci_pci_init(PCIDevice *dev)
memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
SDHC_REGISTERS_MAP_SIZE);
pci_register_bar(dev, 0, 0, &s->iomem);
return 0;
}
static void sdhci_pci_exit(PCIDevice *dev)
@ -1246,7 +1245,7 @@ static void sdhci_pci_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = sdhci_pci_init;
k->realize = sdhci_pci_realize;
k->exit = sdhci_pci_exit;
k->vendor_id = PCI_VENDOR_ID_REDHAT;
k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI;

1
hw/tpm/tpm_int.h
View File

@ -62,6 +62,7 @@ struct tpm_resp_hdr {
#define TPM_FAIL 9
#define TPM_ORD_ContinueSelfTest 0x53
#define TPM_ORD_GetTicks 0xf1
#endif /* TPM_TPM_INT_H */

37
hw/tpm/tpm_passthrough.c
View File

@ -112,14 +112,31 @@ static void tpm_write_fatal_error_response(uint8_t *out, uint32_t out_len)
}
}
static bool tpm_passthrough_is_selftest(const uint8_t *in, uint32_t in_len)
{
struct tpm_req_hdr *hdr = (struct tpm_req_hdr *)in;
if (in_len >= sizeof(*hdr)) {
return (be32_to_cpu(hdr->ordinal) == TPM_ORD_ContinueSelfTest);
}
return false;
}
static int tpm_passthrough_unix_tx_bufs(TPMPassthruState *tpm_pt,
const uint8_t *in, uint32_t in_len,
uint8_t *out, uint32_t out_len)
uint8_t *out, uint32_t out_len,
bool *selftest_done)
{
int ret;
bool is_selftest;
const struct tpm_resp_hdr *hdr;
tpm_pt->tpm_op_canceled = false;
tpm_pt->tpm_executing = true;
*selftest_done = false;
is_selftest = tpm_passthrough_is_selftest(in, in_len);
ret = tpm_passthrough_unix_write(tpm_pt->tpm_fd, in, in_len);
if (ret != in_len) {
@ -149,6 +166,11 @@ static int tpm_passthrough_unix_tx_bufs(TPMPassthruState *tpm_pt,
"packet from TPM\n");
}
if (is_selftest && (ret >= sizeof(struct tpm_resp_hdr))) {
hdr = (struct tpm_resp_hdr *)out;
*selftest_done = (be32_to_cpu(hdr->errcode) == 0);
}
err_exit:
if (ret < 0) {
tpm_write_fatal_error_response(out, out_len);
@ -160,13 +182,15 @@ err_exit:
}
static int tpm_passthrough_unix_transfer(TPMPassthruState *tpm_pt,
const TPMLocality *locty_data)
const TPMLocality *locty_data,
bool *selftest_done)
{
return tpm_passthrough_unix_tx_bufs(tpm_pt,
locty_data->w_buffer.buffer,
locty_data->w_offset,
locty_data->r_buffer.buffer,
locty_data->r_buffer.size);
locty_data->r_buffer.size,
selftest_done);
}
static void tpm_passthrough_worker_thread(gpointer data,
@ -175,16 +199,19 @@ static void tpm_passthrough_worker_thread(gpointer data,
TPMPassthruThreadParams *thr_parms = user_data;
TPMPassthruState *tpm_pt = TPM_PASSTHROUGH(thr_parms->tb);
TPMBackendCmd cmd = (TPMBackendCmd)data;
bool selftest_done = false;
DPRINTF("tpm_passthrough: processing command type %d\n", cmd);
switch (cmd) {
case TPM_BACKEND_CMD_PROCESS_CMD:
tpm_passthrough_unix_transfer(tpm_pt,
thr_parms->tpm_state->locty_data);
thr_parms->tpm_state->locty_data,
&selftest_done);
thr_parms->recv_data_callback(thr_parms->tpm_state,
thr_parms->tpm_state->locty_number);
thr_parms->tpm_state->locty_number,
selftest_done);
break;
case TPM_BACKEND_CMD_INIT:
case TPM_BACKEND_CMD_END:

131
hw/tpm/tpm_tis.c
View File

@ -14,7 +14,7 @@
*
* Implementation of the TIS interface according to specs found at
* http://www.trustedcomputinggroup.org. This implementation currently
* supports version 1.21, revision 1.0.
* supports version 1.3, 21 March 2013
* In the developers menu choose the PC Client section then find the TIS
* specification.
*/
@ -51,6 +51,8 @@
#define TPM_TIS_REG_INTF_CAPABILITY 0x14
#define TPM_TIS_REG_STS 0x18
#define TPM_TIS_REG_DATA_FIFO 0x24
#define TPM_TIS_REG_DATA_XFIFO 0x80
#define TPM_TIS_REG_DATA_XFIFO_END 0xbc
#define TPM_TIS_REG_DID_VID 0xf00
#define TPM_TIS_REG_RID 0xf04
@ -62,6 +64,7 @@
#define TPM_TIS_STS_TPM_GO (1 << 5)
#define TPM_TIS_STS_DATA_AVAILABLE (1 << 4)
#define TPM_TIS_STS_EXPECT (1 << 3)
#define TPM_TIS_STS_SELFTEST_DONE (1 << 2)
#define TPM_TIS_STS_RESPONSE_RETRY (1 << 1)
#define TPM_TIS_BURST_COUNT_SHIFT 8
@ -100,8 +103,15 @@
#endif
#define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28)
#define TPM_TIS_CAP_DATA_TRANSFER_64B (3 << 9)
#define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9)
#define TPM_TIS_CAP_BURST_COUNT_DYNAMIC (0 << 8)
#define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL (1 << 4) /* support is mandatory */
#define TPM_TIS_CAPABILITIES_SUPPORTED (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \
TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \
TPM_TIS_CAP_DATA_TRANSFER_64B | \
TPM_TIS_CAP_INTERFACE_VERSION1_3 | \
TPM_TIS_INTERRUPTS_SUPPORTED)
#define TPM_TIS_TPM_DID 0x0001
@ -144,6 +154,24 @@ static void tpm_tis_show_buffer(const TPMSizedBuffer *sb, const char *string)
#endif
}
/*
* Set the given flags in the STS register by clearing the register but
* preserving the SELFTEST_DONE flag and then setting the new flags.
*
* The SELFTEST_DONE flag is acquired from the backend that determines it by
* peeking into TPM commands.
*
* A VM suspend/resume will preserve the flag by storing it into the VM
* device state, but the backend will not remember it when QEMU is started
* again. Therefore, we cache the flag here. Once set, it will not be unset
* except by a reset.
*/
static void tpm_tis_sts_set(TPMLocality *l, uint32_t flags)
{
l->sts &= TPM_TIS_STS_SELFTEST_DONE;
l->sts |= flags;
}
/*
* Send a request to the TPM.
*/
@ -255,7 +283,8 @@ static void tpm_tis_abort(TPMState *s, uint8_t locty)
*/
if (tis->aborting_locty == tis->next_locty) {
tis->loc[tis->aborting_locty].state = TPM_TIS_STATE_READY;
tis->loc[tis->aborting_locty].sts = TPM_TIS_STS_COMMAND_READY;
tpm_tis_sts_set(&tis->loc[tis->aborting_locty],
TPM_TIS_STS_COMMAND_READY);
tpm_tis_raise_irq(s, tis->aborting_locty, TPM_TIS_INT_COMMAND_READY);
}
@ -300,7 +329,8 @@ static void tpm_tis_receive_bh(void *opaque)
TPMTISEmuState *tis = &s->s.tis;
uint8_t locty = s->locty_number;
tis->loc[locty].sts = TPM_TIS_STS_VALID | TPM_TIS_STS_DATA_AVAILABLE;
tpm_tis_sts_set(&tis->loc[locty],
TPM_TIS_STS_VALID | TPM_TIS_STS_DATA_AVAILABLE);
tis->loc[locty].state = TPM_TIS_STATE_COMPLETION;
tis->loc[locty].r_offset = 0;
tis->loc[locty].w_offset = 0;
@ -320,12 +350,20 @@ static void tpm_tis_receive_bh(void *opaque)
/*
* Callback from the TPM to indicate that the response was received.
*/
static void tpm_tis_receive_cb(TPMState *s, uint8_t locty)
static void tpm_tis_receive_cb(TPMState *s, uint8_t locty,
bool is_selftest_done)
{
TPMTISEmuState *tis = &s->s.tis;
uint8_t l;
assert(s->locty_number == locty);
if (is_selftest_done) {
for (l = 0; l < TPM_TIS_NUM_LOCALITIES; l++) {
tis->loc[locty].sts |= TPM_TIS_STS_SELFTEST_DONE;
}
}
qemu_bh_schedule(tis->bh);
}
@ -344,7 +382,7 @@ static uint32_t tpm_tis_data_read(TPMState *s, uint8_t locty)
ret = tis->loc[locty].r_buffer.buffer[tis->loc[locty].r_offset++];
if (tis->loc[locty].r_offset >= len) {
/* got last byte */
tis->loc[locty].sts = TPM_TIS_STS_VALID;
tpm_tis_sts_set(&tis->loc[locty], TPM_TIS_STS_VALID);
#ifdef RAISE_STS_IRQ
tpm_tis_raise_irq(s, locty, TPM_TIS_INT_STS_VALID);
#endif
@ -427,6 +465,7 @@ static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr,
uint32_t val = 0xffffffff;
uint8_t locty = tpm_tis_locality_from_addr(addr);
uint32_t avail;
uint8_t v;
if (tpm_backend_had_startup_error(s->be_driver)) {
return val;
@ -475,15 +514,28 @@ static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr,
}
break;
case TPM_TIS_REG_DATA_FIFO:
case TPM_TIS_REG_DATA_XFIFO ... TPM_TIS_REG_DATA_XFIFO_END:
if (tis->active_locty == locty) {
switch (tis->loc[locty].state) {
case TPM_TIS_STATE_COMPLETION:
val = tpm_tis_data_read(s, locty);
break;
default:
val = TPM_TIS_NO_DATA_BYTE;
break;
if (size > 4 - (addr & 0x3)) {
/* prevent access beyond FIFO */
size = 4 - (addr & 0x3);
}
val = 0;
shift = 0;
while (size > 0) {
switch (tis->loc[locty].state) {
case TPM_TIS_STATE_COMPLETION:
v = tpm_tis_data_read(s, locty);
break;
default:
v = TPM_TIS_NO_DATA_BYTE;
break;
}
val |= (v << shift);
shift += 8;
size--;
}
shift = 0; /* no more adjustments */
}
break;
case TPM_TIS_REG_DID_VID:
@ -518,11 +570,13 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr,
{
TPMState *s = opaque;
TPMTISEmuState *tis = &s->s.tis;
uint16_t off = addr & 0xfff;
uint16_t off = addr & 0xffc;
uint8_t shift = (addr & 0x3) * 8;
uint8_t locty = tpm_tis_locality_from_addr(addr);
uint8_t active_locty, l;
int c, set_new_locty = 1;
uint16_t len;
uint32_t mask = (size == 1) ? 0xff : ((size == 2) ? 0xffff : ~0);
DPRINTF("tpm_tis: write.%u(%08x) = %08x\n", size, (int)addr, (uint32_t)val);
@ -535,6 +589,15 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr,
return;
}
val &= mask;
if (shift) {
val <<= shift;
mask <<= shift;
}
mask ^= 0xffffffff;
switch (off) {
case TPM_TIS_REG_ACCESS:
@ -646,9 +709,10 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr,
break;
}
tis->loc[locty].inte = (val & (TPM_TIS_INT_ENABLED |
TPM_TIS_INT_POLARITY_MASK |
TPM_TIS_INTERRUPTS_SUPPORTED));
tis->loc[locty].inte &= mask;
tis->loc[locty].inte |= (val & (TPM_TIS_INT_ENABLED |
TPM_TIS_INT_POLARITY_MASK |
TPM_TIS_INTERRUPTS_SUPPORTED));
break;
case TPM_TIS_REG_INT_VECTOR:
/* hard wired -- ignore */
@ -686,7 +750,7 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr,
break;
case TPM_TIS_STATE_IDLE:
tis->loc[locty].sts = TPM_TIS_STS_COMMAND_READY;
tpm_tis_sts_set(&tis->loc[locty], TPM_TIS_STS_COMMAND_READY);
tis->loc[locty].state = TPM_TIS_STATE_READY;
tpm_tis_raise_irq(s, locty, TPM_TIS_INT_COMMAND_READY);
break;
@ -705,7 +769,8 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr,
/* shortcut to ready state with C/R set */
tis->loc[locty].state = TPM_TIS_STATE_READY;
if (!(tis->loc[locty].sts & TPM_TIS_STS_COMMAND_READY)) {
tis->loc[locty].sts = TPM_TIS_STS_COMMAND_READY;
tpm_tis_sts_set(&tis->loc[locty],
TPM_TIS_STS_COMMAND_READY);
tpm_tis_raise_irq(s, locty, TPM_TIS_INT_COMMAND_READY);
}
tis->loc[locty].sts &= ~(TPM_TIS_STS_DATA_AVAILABLE);
@ -727,8 +792,9 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr,
switch (tis->loc[locty].state) {
case TPM_TIS_STATE_COMPLETION:
tis->loc[locty].r_offset = 0;
tis->loc[locty].sts = TPM_TIS_STS_VALID |
TPM_TIS_STS_DATA_AVAILABLE;
tpm_tis_sts_set(&tis->loc[locty],
TPM_TIS_STS_VALID|
TPM_TIS_STS_DATA_AVAILABLE);
break;
default:
/* ignore */
@ -737,6 +803,7 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr,
}
break;
case TPM_TIS_REG_DATA_FIFO:
case TPM_TIS_REG_DATA_XFIFO ... TPM_TIS_REG_DATA_XFIFO_END:
/* data fifo */
if (tis->active_locty != locty) {
break;
@ -747,18 +814,28 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr,
tis->loc[locty].state == TPM_TIS_STATE_COMPLETION) {
/* drop the byte */
} else {
DPRINTF("tpm_tis: Byte to send to TPM: %02x\n", (uint8_t)val);
DPRINTF("tpm_tis: Data to send to TPM: %08x (size=%d)\n",
val, size);
if (tis->loc[locty].state == TPM_TIS_STATE_READY) {
tis->loc[locty].state = TPM_TIS_STATE_RECEPTION;
tis->loc[locty].sts = TPM_TIS_STS_EXPECT | TPM_TIS_STS_VALID;
tpm_tis_sts_set(&tis->loc[locty],
TPM_TIS_STS_EXPECT | TPM_TIS_STS_VALID);
}
if ((tis->loc[locty].sts & TPM_TIS_STS_EXPECT)) {
val >>= shift;
if (size > 4 - (addr & 0x3)) {
/* prevent access beyond FIFO */
size = 4 - (addr & 0x3);
}
while ((tis->loc[locty].sts & TPM_TIS_STS_EXPECT) && size > 0) {
if (tis->loc[locty].w_offset < tis->loc[locty].w_buffer.size) {
tis->loc[locty].w_buffer.
buffer[tis->loc[locty].w_offset++] = (uint8_t)val;
val >>= 8;
size--;
} else {
tis->loc[locty].sts = TPM_TIS_STS_VALID;
tpm_tis_sts_set(&tis->loc[locty], TPM_TIS_STS_VALID);
}
}
@ -771,11 +848,11 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr,
#endif
len = tpm_tis_get_size_from_buffer(&tis->loc[locty].w_buffer);
if (len > tis->loc[locty].w_offset) {
tis->loc[locty].sts = TPM_TIS_STS_EXPECT |
TPM_TIS_STS_VALID;
tpm_tis_sts_set(&tis->loc[locty],
TPM_TIS_STS_EXPECT | TPM_TIS_STS_VALID);
} else {
/* packet complete */
tis->loc[locty].sts = TPM_TIS_STS_VALID;
tpm_tis_sts_set(&tis->loc[locty], TPM_TIS_STS_VALID);
}
#ifdef RAISE_STS_IRQ
if (needIrq) {

2
hw/tpm/tpm_tis.h
View File

@ -41,7 +41,7 @@ typedef enum {
typedef struct TPMLocality {
TPMTISState state;
uint8_t access;
uint8_t sts;
uint32_t sts;
uint32_t inte;
uint32_t ints;

6
hw/usb/hcd-ehci-pci.c
View File

@ -26,7 +26,7 @@ typedef struct EHCIPCIInfo {
bool companion;
} EHCIPCIInfo;
static int usb_ehci_pci_initfn(PCIDevice *dev)
static void usb_ehci_pci_realize(PCIDevice *dev, Error **errp)
{
EHCIPCIState *i = PCI_EHCI(dev);
EHCIState *s = &i->ehci;
@ -66,8 +66,6 @@ static int usb_ehci_pci_initfn(PCIDevice *dev)
usb_ehci_realize(s, DEVICE(dev), NULL);
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
return 0;
}
static void usb_ehci_pci_init(Object *obj)
@ -139,7 +137,7 @@ static void ehci_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = usb_ehci_pci_initfn;
k->realize = usb_ehci_pci_realize;
k->exit = usb_ehci_pci_exit;
k->class_id = PCI_CLASS_SERIAL_USB;
k->config_write = usb_ehci_pci_write_config;

6
hw/usb/hcd-xhci.c
View File

@ -3576,7 +3576,7 @@ static void usb_xhci_init(XHCIState *xhci)
}
}
static int usb_xhci_initfn(struct PCIDevice *dev)
static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
{
int i, ret;
@ -3655,8 +3655,6 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
&xhci->mem, 0, OFF_MSIX_PBA,
0x90);
}
return 0;
}
static void usb_xhci_exit(PCIDevice *dev)
@ -3896,7 +3894,7 @@ static void xhci_class_init(ObjectClass *klass, void *data)
dc->props = xhci_properties;
dc->reset = xhci_reset;
set_bit(DEVICE_CATEGORY_USB, dc->categories);
k->init = usb_xhci_initfn;
k->realize = usb_xhci_realize;
k->exit = usb_xhci_exit;
k->vendor_id = PCI_VENDOR_ID_NEC;
k->device_id = PCI_DEVICE_ID_NEC_UPD720200;

10
hw/virtio/dataplane/vring.c
View File

@ -105,7 +105,7 @@ void vring_teardown(Vring *vring, VirtIODevice *vdev, int n)
/* Disable guest->host notifies */
void vring_disable_notification(VirtIODevice *vdev, Vring *vring)
{
if (!(vdev->guest_features & (1 << VIRTIO_RING_F_EVENT_IDX))) {
if (!virtio_has_feature(vdev, VIRTIO_RING_F_EVENT_IDX)) {
vring_set_used_flags(vdev, vring, VRING_USED_F_NO_NOTIFY);
}
}
@ -116,7 +116,7 @@ void vring_disable_notification(VirtIODevice *vdev, Vring *vring)
*/
bool vring_enable_notification(VirtIODevice *vdev, Vring *vring)
{
if (vdev->guest_features & (1 << VIRTIO_RING_F_EVENT_IDX)) {
if (virtio_has_feature(vdev, VIRTIO_RING_F_EVENT_IDX)) {
vring_avail_event(&vring->vr) = vring->vr.avail->idx;
} else {
vring_clear_used_flags(vdev, vring, VRING_USED_F_NO_NOTIFY);
@ -135,12 +135,12 @@ bool vring_should_notify(VirtIODevice *vdev, Vring *vring)
* interrupts. */
smp_mb();
if ((vdev->guest_features & (1 << VIRTIO_F_NOTIFY_ON_EMPTY)) &&
if (virtio_has_feature(vdev, VIRTIO_F_NOTIFY_ON_EMPTY) &&
unlikely(!vring_more_avail(vdev, vring))) {
return true;
}
if (!(vdev->guest_features & (1 << VIRTIO_RING_F_EVENT_IDX))) {
if (!virtio_has_feature(vdev, VIRTIO_RING_F_EVENT_IDX)) {
return !(vring_get_avail_flags(vdev, vring) &
VRING_AVAIL_F_NO_INTERRUPT);
}
@ -401,7 +401,7 @@ int vring_pop(VirtIODevice *vdev, Vring *vring,
/* On success, increment avail index. */
vring->last_avail_idx++;
if (vdev->guest_features & (1 << VIRTIO_RING_F_EVENT_IDX)) {
if (virtio_has_feature(vdev, VIRTIO_RING_F_EVENT_IDX)) {
vring_avail_event(&vring->vr) = vring->last_avail_idx;
}

2
hw/virtio/virtio-balloon.c
View File

@ -70,7 +70,7 @@ static inline void reset_stats(VirtIOBalloon *dev)
static bool balloon_stats_supported(const VirtIOBalloon *s)
{
VirtIODevice *vdev = VIRTIO_DEVICE(s);
return vdev->guest_features & (1 << VIRTIO_BALLOON_F_STATS_VQ);
return virtio_has_feature(vdev, VIRTIO_BALLOON_F_STATS_VQ);
}
static bool balloon_stats_enabled(const VirtIOBalloon *s)

14
hw/virtio/virtio-bus.c
View File

@ -109,20 +109,6 @@ uint32_t virtio_bus_get_vdev_features(VirtioBusState *bus,
return k->get_features(vdev, requested_features);
}
/* Set the features of the plugged device. */
void virtio_bus_set_vdev_features(VirtioBusState *bus,
uint32_t requested_features)
{
VirtIODevice *vdev = virtio_bus_get_device(bus);
VirtioDeviceClass *k;
assert(vdev != NULL);
k = VIRTIO_DEVICE_GET_CLASS(vdev);
if (k->set_features != NULL) {
k->set_features(vdev, requested_features);
}
}
/* Get bad features of the plugged device. */
uint32_t virtio_bus_get_vdev_bad_features(VirtioBusState *bus)
{

2
hw/virtio/virtio-mmio.c
View File

@ -349,7 +349,7 @@ static void virtio_mmio_device_plugged(DeviceState *opaque)
{
VirtIOMMIOProxy *proxy = VIRTIO_MMIO(opaque);
proxy->host_features |= (0x1 << VIRTIO_F_NOTIFY_ON_EMPTY);
virtio_add_feature(&proxy->host_features, VIRTIO_F_NOTIFY_ON_EMPTY);
proxy->host_features = virtio_bus_get_vdev_features(&proxy->bus,
proxy->host_features);
}

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