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hw/pci-host/piix: Move RCR_IOPORT register definition

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The RCR_IOPORT register belongs to the PIIX chipset.
Move the definition to "piix.h", and prepend the PIIX prefix.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé 2019-02-02 20:48:46 +01:00 committed by Philippe Mathieu-Daudé
parent b7d255e103
commit 0063454aff
5 changed files with 12 additions and 11 deletions
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2
hw/i386/acpi-build.c
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@ -209,7 +209,7 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
/* The above need not be conditional on machine type because the reset port /* The above need not be conditional on machine type because the reset port
* happens to be the same on PIIX (pc) and ICH9 (q35). */ * happens to be the same on PIIX (pc) and ICH9 (q35). */
QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT); QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
/* Fill in optional s3/s4 related properties */ /* Fill in optional s3/s4 related properties */
o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);

2
hw/isa/piix4.c
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@ -166,7 +166,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
"reset-control", 1); "reset-control", 1);
memory_region_add_subregion_overlap(pci_address_space_io(dev), memory_region_add_subregion_overlap(pci_address_space_io(dev),
RCR_IOPORT, &s->rcr_mem, 1); PIIX_RCR_IOPORT, &s->rcr_mem, 1);
/* initialize i8259 pic */ /* initialize i8259 pic */
i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);

7
hw/pci-host/piix.c
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@ -27,6 +27,7 @@
#include "hw/irq.h" #include "hw/irq.h"
#include "hw/pci/pci.h" #include "hw/pci/pci.h"
#include "hw/pci/pci_host.h" #include "hw/pci/pci_host.h"
#include "hw/southbridge/piix.h"
#include "hw/qdev-properties.h" #include "hw/qdev-properties.h"
#include "hw/isa/isa.h" #include "hw/isa/isa.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
@ -87,7 +88,7 @@ typedef struct PIIX3State {
/* Reset Control Register contents */ /* Reset Control Register contents */
uint8_t rcr; uint8_t rcr;
/* IO memory region for Reset Control Register (RCR_IOPORT) */ /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
MemoryRegion rcr_mem; MemoryRegion rcr_mem;
} PIIX3State; } PIIX3State;
@ -695,8 +696,8 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
"piix3-reset-control", 1); "piix3-reset-control", 1);
memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT, memory_region_add_subregion_overlap(pci_address_space_io(dev),
&d->rcr_mem, 1); PIIX_RCR_IOPORT, &d->rcr_mem, 1);
qemu_register_reset(piix3_reset, d); qemu_register_reset(piix3_reset, d);
} }

6
include/hw/i386/pc.h
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@ -240,12 +240,6 @@ typedef struct PCII440FXState PCII440FXState;
#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
/*
* Reset Control Register: PCI-accessible ISA-Compatible Register at address
* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
*/
#define RCR_IOPORT 0xcf9
PCIBus *i440fx_init(const char *host_type, const char *pci_type, PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCII440FXState **pi440fx_state, int *piix_devfn, PCII440FXState **pi440fx_state, int *piix_devfn,
ISABus **isa_bus, qemu_irq *pic, ISABus **isa_bus, qemu_irq *pic,

6
include/hw/southbridge/piix.h
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@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq, qemu_irq sci_irq, qemu_irq smi_irq,
int smm_enabled, DeviceState **piix4_pm); int smm_enabled, DeviceState **piix4_pm);
/*
* Reset Control Register: PCI-accessible ISA-Compatible Register at address
* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
*/
#define PIIX_RCR_IOPORT 0xcf9
extern PCIDevice *piix4_dev; extern PCIDevice *piix4_dev;
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,