From 0259e96687fa9b01d87113693e076dfa83a649f0 Mon Sep 17 00:00:00 2001 From: Laszlo Ersek Date: Thu, 27 Sep 2018 23:24:36 +0200 Subject: [PATCH] tests/bios-tables-test: add 64-bit PCI MMIO aperture round-up test on Q35 In commit 9fa99d2519cb ("hw/pci-host: Fix x86 Host Bridges 64bit PCI hole", 2017-11-16), we meant to expose such a 64-bit PCI MMIO aperture in the ACPI DSDT that would be at least as large as the new "pci-hole64-size" property (2GB on i440fx, 32GB on q35). The goal was to offer "enough" 64-bit MMIO aperture to the guest OS for hotplug purposes. Previous patch fixed the issue that the aperture is extended relative to a possibly incorrect base. This may result in an aperture size that is smaller than the intent of commit 9fa99d2519cb. This patch adds a test to make sure it won't happen again. In the test case being added: - use 128 MB initial RAM size, - ask for one DIMM hotplug slot, - ask for 2 GB maximum RAM size, - use a pci-testdev with a 64-bit BAR of 2 GB size. Consequences: (1) In pc_memory_init() [hw/i386/pc.c], the DIMM hotplug area size is initially set to 2048-128 = 1920 MB. (Maximum RAM size minus initial RAM size.) (2) The DIMM area base is set to 4096 MB (because the initial RAM is only 128 MB -- there is no initial "high RAM"). (3) Due to commit 085f8e88ba73 ("pc: count in 1Gb hugepage alignment when sizing hotplug-memory container", 2014-11-24), we add 1 GB for the one DIMM hotplug slot that was specified. This sets the DIMM area size to 1920+1024 = 2944 MB. (4) The reserved-memory-end address (exclusive) is set to 4096 + 2944 = 7040 MB (DIMM area base plus DIMM area size). (5) The reserved-memory-end address is rounded up to GB alignment, yielding 7 GB (7168 MB). (6) Given the 2 GB BAR size of pci-testdev, SeaBIOS allocates said 64-bit BAR in 64-bit address space. (7) Because reserved-memory-end is at 7 GB, it is unaligned for the 2 GB BAR. Therefore SeaBIOS allocates the BAR at 8 GB. QEMU then (correctly) assigns the root bridge aperture base this BAR address, to be exposed in \_SB.PCI0._CRS. (8) The intent of commit 9fa99d2519cb dictates that QEMU extend the aperture size to 32 GB, implying a 40 GB end address. However, QEMU performs the extension relative to reserved-memory-end (7 GB), not relative to the bridge aperture base that was correctly deduced from SeaBIOS's BAR programming (8 GB). Therefore we see 39 GB as the aperture end address in \_SB.PCI0._CRS: > QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, > 0x0000000000000000, // Granularity > 0x0000000200000000, // Range Minimum > 0x00000009BFFFFFFF, // Range Maximum > 0x0000000000000000, // Translation Offset > 0x00000007C0000000, // Length > ,, , AddressRangeMemory, TypeStatic) Cc: "Michael S. Tsirkin" Cc: Alex Williamson Cc: Gerd Hoffmann Cc: Igor Mammedov Cc: Marcel Apfelbaum Signed-off-by: Laszlo Ersek Reviewed-by: Marcel Apfelbaum Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/bios-tables-test.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c index b14c8eaa17..d661d9be62 100644 --- a/tests/bios-tables-test.c +++ b/tests/bios-tables-test.c @@ -708,6 +708,21 @@ static void test_acpi_q35_tcg_bridge(void) free_test_data(&data); } +static void test_acpi_q35_tcg_mmio64(void) +{ + test_data data = { + .machine = MACHINE_Q35, + .variant = ".mmio64", + .required_struct_types = base_required_struct_types, + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types) + }; + + test_acpi_one("-m 128M,slots=1,maxmem=2G " + "-device pci-testdev,membar=2G", + &data); + free_test_data(&data); +} + static void test_acpi_piix4_tcg_cphp(void) { test_data data; @@ -875,6 +890,7 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/piix4/bridge", test_acpi_piix4_tcg_bridge); qtest_add_func("acpi/q35", test_acpi_q35_tcg); qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge); + qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64); qtest_add_func("acpi/piix4/ipmi", test_acpi_piix4_tcg_ipmi); qtest_add_func("acpi/q35/ipmi", test_acpi_q35_tcg_ipmi); qtest_add_func("acpi/piix4/cpuhp", test_acpi_piix4_tcg_cphp);