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target-arm: Add IRQ and FIQ routing to EL2 and 3

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Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1411718914-6608-11-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Edgar E. Iglesias 2014-09-29 18:48:51 +01:00 committed by Peter Maydell
parent e0d6e6a5e7
commit 041c96666d
2 changed files with 27 additions and 0 deletions
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10
target-arm/cpu.h
View File

@ -1180,6 +1180,10 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx)
CPUARMState *env = cs->env_ptr; CPUARMState *env = cs->env_ptr;
unsigned int cur_el = arm_current_pl(env); unsigned int cur_el = arm_current_pl(env);
unsigned int target_el = arm_excp_target_el(cs, excp_idx); unsigned int target_el = arm_excp_target_el(cs, excp_idx);
/* FIXME: Use actual secure state. */
bool secure = false;
/* If in EL1/0, Physical IRQ routing to EL2 only happens from NS state. */
bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2;
/* Don't take exceptions if they target a lower EL. */ /* Don't take exceptions if they target a lower EL. */
if (cur_el > target_el) { if (cur_el > target_el) {
@ -1188,8 +1192,14 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx)
switch (excp_idx) { switch (excp_idx) {
case EXCP_FIQ: case EXCP_FIQ:
if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_FMO)) {
return true;
}
return !(env->daif & PSTATE_F); return !(env->daif & PSTATE_F);
case EXCP_IRQ: case EXCP_IRQ:
if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) {
return true;
}
return !(env->daif & PSTATE_I) return !(env->daif & PSTATE_I)
&& (!IS_M(env) || env->regs[15] < 0xfffffff0); && (!IS_M(env) || env->regs[15] < 0xfffffff0);
default: default:

17
target-arm/helper.c
View File

@ -3773,6 +3773,8 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
CPUARMState *env = &cpu->env; CPUARMState *env = &cpu->env;
unsigned int cur_el = arm_current_pl(env); unsigned int cur_el = arm_current_pl(env);
unsigned int target_el; unsigned int target_el;
/* FIXME: Use actual secure state. */
bool secure = false;
if (!env->aarch64) { if (!env->aarch64) {
/* TODO: Add EL2 and 3 exception handling for AArch32. */ /* TODO: Add EL2 and 3 exception handling for AArch32. */
@ -3787,6 +3789,21 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
case EXCP_SMC: case EXCP_SMC:
target_el = 3; target_el = 3;
break; break;
case EXCP_FIQ:
case EXCP_IRQ:
{
const uint64_t hcr_mask = excp_idx == EXCP_FIQ ? HCR_FMO : HCR_IMO;
const uint32_t scr_mask = excp_idx == EXCP_FIQ ? SCR_FIQ : SCR_IRQ;
target_el = 1;
if (!secure && (env->cp15.hcr_el2 & hcr_mask)) {
target_el = 2;
}
if (env->cp15.scr_el3 & scr_mask) {
target_el = 3;
}
break;
}
default: default:
target_el = MAX(cur_el, 1); target_el = MAX(cur_el, 1);
break; break;