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Xen 2015/12/22
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJWeXe1AAoJEIlPj0hw4a6QpTUQAPirj6gWanKtVTRGPnOhClMW h9inFwkoAxQj5KGYeiI8RYzrWhFKDooOe4T+qIenp6HYMzQdSpM1A/wEeO6UnyVw j3hEI6bi+ZNG27yEJV2mygSY4ivNG7gk2dbKRwqaA2pmbrNEtMTdv45MQYrQeqjC vd6uy+VoZSuG/spQGhGc5JhoYiFFWHzprueqfHsFO8nM+7htRxBne7zw2iB17o9q pptOoETfV6mjbdqxDHKlRnm5DtvXpyszDFtFp3utzjAbsTkrMTxb2iaS+p359fav 6QweJQgrnDKIR1v3VWhs054OmoY9jcW4Q6lnqu7TJbVuOKnlS9Hoe70A0s+knZsz 7HDz73GEjB2rgK0KArK7sOS2/M5lQRj1JbtbzLLkWmq9lndRLgRj6+QoZ72gLs2S +s5X5c1iXLhZtBmGAz/sH6u5A1Bk7YVGHuEN9evfDsIC/uxVGhNX+exXgy0pADG0 iT0+BPKGVTKbZmxYiyfhhMsEiTdcQTI9/KYT+sDHy/9PTaqS6D8rFRHnrZi6PWRn get5L3ZRQ686KcyEh8pQVYpki+HUWStqVlvufvbPkJ0Wpaj9yi6KdlmQOA3IrWni syFd6KJuumtUrX/xISuY+kpG6FlsDHQzh318NEmjU9jFhoKE34JHqtd/C/RMAWKF FdbVufoH+Rq/yQy2QNqE =FXtN -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/sstabellini/tags/xen-2015-12-22' into staging Xen 2015/12/22 # gpg: Signature made Tue 22 Dec 2015 16:17:57 GMT using RSA key ID 70E1AE90 # gpg: Good signature from "Stefano Stabellini <stefano.stabellini@eu.citrix.com>" * remotes/sstabellini/tags/xen-2015-12-22: xen_disk: treat "vhd" as "vpc" xen/pass-through: correctly deal with RW1C bits xen/MSI-X: really enforce alignment xen/MSI-X: latch MSI-X table writes Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
05bec7eb0e
@ -825,6 +825,9 @@ static int blk_init(struct XenDevice *xendev)
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if (!strcmp("aio", blkdev->fileproto)) {
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blkdev->fileproto = "raw";
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}
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if (!strcmp("vhd", blkdev->fileproto)) {
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blkdev->fileproto = "vpc";
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}
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if (blkdev->mode == NULL) {
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blkdev->mode = xenstore_read_be_str(&blkdev->xendev, "mode");
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}
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@ -113,6 +113,8 @@ struct XenPTRegInfo {
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uint32_t res_mask;
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/* reg read only field mask (ON:RO/ROS, OFF:other) */
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uint32_t ro_mask;
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/* reg read/write-1-clear field mask (ON:RW1C/RW1CS, OFF:other) */
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uint32_t rw1c_mask;
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/* reg emulate field mask (ON:emu, OFF:passthrough) */
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uint32_t emu_mask;
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xen_pt_conf_reg_init init;
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@ -187,13 +189,13 @@ typedef struct XenPTMSIXEntry {
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int pirq;
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uint64_t addr;
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uint32_t data;
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uint32_t vector_ctrl;
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uint32_t latch[4];
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bool updated; /* indicate whether MSI ADDR or DATA is updated */
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bool warned; /* avoid issuing (bogus) warning more than once */
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} XenPTMSIXEntry;
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typedef struct XenPTMSIX {
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uint32_t ctrl_offset;
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bool enabled;
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bool maskall;
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int total_entries;
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int bar_index;
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uint64_t table_base;
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@ -179,7 +179,8 @@ static int xen_pt_byte_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
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*data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
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/* create value for writing to I/O device register */
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*val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
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*val = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask,
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throughable_mask);
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return 0;
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}
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@ -197,7 +198,8 @@ static int xen_pt_word_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
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*data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
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/* create value for writing to I/O device register */
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*val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
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*val = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask,
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throughable_mask);
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return 0;
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}
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@ -215,7 +217,8 @@ static int xen_pt_long_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
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*data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
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/* create value for writing to I/O device register */
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*val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
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*val = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask,
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throughable_mask);
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return 0;
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}
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@ -633,6 +636,7 @@ static XenPTRegInfo xen_pt_emu_reg_header0[] = {
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.init_val = 0x0000,
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.res_mask = 0x0007,
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.ro_mask = 0x06F8,
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.rw1c_mask = 0xF900,
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.emu_mask = 0x0010,
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.init = xen_pt_status_reg_init,
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.u.w.read = xen_pt_word_reg_read,
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@ -944,6 +948,7 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
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.size = 2,
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.res_mask = 0xFFC0,
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.ro_mask = 0x0030,
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.rw1c_mask = 0x000F,
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.init = xen_pt_common_reg_init,
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.u.w.read = xen_pt_word_reg_read,
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.u.w.write = xen_pt_word_reg_write,
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@ -964,6 +969,7 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
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.offset = PCI_EXP_LNKSTA,
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.size = 2,
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.ro_mask = 0x3FFF,
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.rw1c_mask = 0xC000,
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.init = xen_pt_common_reg_init,
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.u.w.read = xen_pt_word_reg_read,
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.u.w.write = xen_pt_word_reg_write,
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@ -1000,27 +1006,6 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
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* Power Management Capability
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*/
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/* write Power Management Control/Status register */
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static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState *s,
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XenPTReg *cfg_entry, uint16_t *val,
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uint16_t dev_value, uint16_t valid_mask)
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{
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XenPTRegInfo *reg = cfg_entry->reg;
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uint16_t writable_mask = 0;
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uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
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uint16_t *data = cfg_entry->ptr.half_word;
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/* modify emulate register */
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writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
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*data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
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/* create value for writing to I/O device register */
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*val = XEN_PT_MERGE_VALUE(*val, dev_value & ~PCI_PM_CTRL_PME_STATUS,
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throughable_mask);
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return 0;
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}
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/* Power Management Capability reg static information table */
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static XenPTRegInfo xen_pt_emu_reg_pm[] = {
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/* Next Pointer reg */
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@ -1051,11 +1036,12 @@ static XenPTRegInfo xen_pt_emu_reg_pm[] = {
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.size = 2,
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.init_val = 0x0008,
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.res_mask = 0x00F0,
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.ro_mask = 0xE10C,
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.ro_mask = 0x610C,
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.rw1c_mask = 0x8000,
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.emu_mask = 0x810B,
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.init = xen_pt_common_reg_init,
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.u.w.read = xen_pt_word_reg_read,
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.u.w.write = xen_pt_pmcsr_reg_write,
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.u.w.write = xen_pt_word_reg_write,
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},
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{
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.size = 0,
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@ -1499,6 +1485,8 @@ static int xen_pt_msixctrl_reg_write(XenPCIPassthroughState *s,
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xen_pt_msix_disable(s);
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}
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s->msix->maskall = *val & PCI_MSIX_FLAGS_MASKALL;
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debug_msix_enabled_old = s->msix->enabled;
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s->msix->enabled = !!(*val & PCI_MSIX_FLAGS_ENABLE);
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if (s->msix->enabled != debug_msix_enabled_old) {
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@ -25,6 +25,7 @@
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#define XEN_PT_GFLAGSSHIFT_DELIV_MODE 12
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#define XEN_PT_GFLAGSSHIFT_TRG_MODE 15
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#define latch(fld) latch[PCI_MSIX_ENTRY_##fld / sizeof(uint32_t)]
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/*
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* Helpers
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@ -314,7 +315,8 @@ static int msix_set_enable(XenPCIPassthroughState *s, bool enabled)
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enabled);
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}
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static int xen_pt_msix_update_one(XenPCIPassthroughState *s, int entry_nr)
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static int xen_pt_msix_update_one(XenPCIPassthroughState *s, int entry_nr,
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uint32_t vec_ctrl)
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{
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XenPTMSIXEntry *entry = NULL;
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int pirq;
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@ -332,6 +334,19 @@ static int xen_pt_msix_update_one(XenPCIPassthroughState *s, int entry_nr)
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pirq = entry->pirq;
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/*
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* Update the entry addr and data to the latest values only when the
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* entry is masked or they are all masked, as required by the spec.
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* Addr and data changes while the MSI-X entry is unmasked get deferred
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* until the next masked -> unmasked transition.
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*/
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if (pirq == XEN_PT_UNASSIGNED_PIRQ || s->msix->maskall ||
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(vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT)) {
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entry->addr = entry->latch(LOWER_ADDR) |
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((uint64_t)entry->latch(UPPER_ADDR) << 32);
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entry->data = entry->latch(DATA);
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}
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rc = msi_msix_setup(s, entry->addr, entry->data, &pirq, true, entry_nr,
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entry->pirq == XEN_PT_UNASSIGNED_PIRQ);
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if (rc) {
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@ -357,7 +372,7 @@ int xen_pt_msix_update(XenPCIPassthroughState *s)
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int i;
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for (i = 0; i < msix->total_entries; i++) {
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xen_pt_msix_update_one(s, i);
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xen_pt_msix_update_one(s, i, msix->msix_entry[i].latch(VECTOR_CTRL));
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}
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return 0;
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@ -406,36 +421,14 @@ int xen_pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index)
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static uint32_t get_entry_value(XenPTMSIXEntry *e, int offset)
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{
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switch (offset) {
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case PCI_MSIX_ENTRY_LOWER_ADDR:
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return e->addr & UINT32_MAX;
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case PCI_MSIX_ENTRY_UPPER_ADDR:
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return e->addr >> 32;
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case PCI_MSIX_ENTRY_DATA:
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return e->data;
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case PCI_MSIX_ENTRY_VECTOR_CTRL:
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return e->vector_ctrl;
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default:
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return 0;
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}
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assert(!(offset % sizeof(*e->latch)));
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return e->latch[offset / sizeof(*e->latch)];
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}
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static void set_entry_value(XenPTMSIXEntry *e, int offset, uint32_t val)
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{
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switch (offset) {
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case PCI_MSIX_ENTRY_LOWER_ADDR:
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e->addr = (e->addr & ((uint64_t)UINT32_MAX << 32)) | val;
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break;
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case PCI_MSIX_ENTRY_UPPER_ADDR:
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e->addr = (uint64_t)val << 32 | (e->addr & UINT32_MAX);
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break;
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case PCI_MSIX_ENTRY_DATA:
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e->data = val;
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break;
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case PCI_MSIX_ENTRY_VECTOR_CTRL:
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e->vector_ctrl = val;
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break;
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}
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assert(!(offset % sizeof(*e->latch)));
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e->latch[offset / sizeof(*e->latch)] = val;
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}
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static void pci_msix_write(void *opaque, hwaddr addr,
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@ -454,39 +447,26 @@ static void pci_msix_write(void *opaque, hwaddr addr,
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offset = addr % PCI_MSIX_ENTRY_SIZE;
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if (offset != PCI_MSIX_ENTRY_VECTOR_CTRL) {
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const volatile uint32_t *vec_ctrl;
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if (get_entry_value(entry, offset) == val
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&& entry->pirq != XEN_PT_UNASSIGNED_PIRQ) {
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return;
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}
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entry->updated = true;
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} else if (msix->enabled && entry->updated &&
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!(val & PCI_MSIX_ENTRY_CTRL_MASKBIT)) {
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const volatile uint32_t *vec_ctrl;
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/*
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* If Xen intercepts the mask bit access, entry->vec_ctrl may not be
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* up-to-date. Read from hardware directly.
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*/
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vec_ctrl = s->msix->phys_iomem_base + entry_nr * PCI_MSIX_ENTRY_SIZE
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+ PCI_MSIX_ENTRY_VECTOR_CTRL;
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if (msix->enabled && !(*vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT)) {
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if (!entry->warned) {
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entry->warned = true;
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XEN_PT_ERR(&s->dev, "Can't update msix entry %d since MSI-X is"
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" already enabled.\n", entry_nr);
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}
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return;
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}
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entry->updated = true;
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xen_pt_msix_update_one(s, entry_nr, *vec_ctrl);
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}
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set_entry_value(entry, offset, val);
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if (offset == PCI_MSIX_ENTRY_VECTOR_CTRL) {
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if (msix->enabled && !(val & PCI_MSIX_ENTRY_CTRL_MASKBIT)) {
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xen_pt_msix_update_one(s, entry_nr);
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}
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}
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}
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static uint64_t pci_msix_read(void *opaque, hwaddr addr,
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@ -512,6 +492,12 @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
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}
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}
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static bool pci_msix_accepts(void *opaque, hwaddr addr,
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unsigned size, bool is_write)
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{
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return !(addr & (size - 1));
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}
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static const MemoryRegionOps pci_msix_ops = {
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.read = pci_msix_read,
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.write = pci_msix_write,
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@ -520,7 +506,13 @@ static const MemoryRegionOps pci_msix_ops = {
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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.accepts = pci_msix_accepts
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false
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}
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};
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int xen_pt_msix_init(XenPCIPassthroughState *s, uint32_t base)
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