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target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc
The functions vfp_load_reg32(), vfp_load_reg64(), vfp_store_reg32() and vfp_store_reg64() are used only in translate-vfp.c.inc. Move them to that file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210430132740.10391-7-peter.maydell@linaro.org
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@ -30,6 +30,26 @@
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#include "decode-vfp.c.inc"
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#include "decode-vfp-uncond.c.inc"
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static inline void vfp_load_reg64(TCGv_i64 var, int reg)
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{
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tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg));
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}
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static inline void vfp_store_reg64(TCGv_i64 var, int reg)
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{
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tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg));
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}
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static inline void vfp_load_reg32(TCGv_i32 var, int reg)
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{
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tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg));
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}
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static inline void vfp_store_reg32(TCGv_i32 var, int reg)
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{
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tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
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}
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/*
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* The imm8 encodes the sign bit, enough bits to represent an exponent in
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* the range 01....1xx to 10....0xx, and the most significant 4 bits of
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@ -1144,26 +1144,6 @@ static long vfp_reg_offset(bool dp, unsigned reg)
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}
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}
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static inline void vfp_load_reg64(TCGv_i64 var, int reg)
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{
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tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg));
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}
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static inline void vfp_store_reg64(TCGv_i64 var, int reg)
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{
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tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg));
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}
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static inline void vfp_load_reg32(TCGv_i32 var, int reg)
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{
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tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg));
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}
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static inline void vfp_store_reg32(TCGv_i32 var, int reg)
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{
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tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
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}
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void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
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{
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long off = neon_element_offset(reg, ele, memop);
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