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target/riscv: trans_rvv: Avoid assert for RV32 and e64

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When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to
true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside
tcg_gen_gvec_dup_i32().

This patch checks that condition and instead uses tcg_gen_gvec_dup_i64()
is required.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1028
Suggested-by: Robert Bu <robert.bu@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220608234701.369536-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alistair Francis 2022-06-09 09:47:01 +10:00
parent 26b2bc5859
commit 07314158f6
1 changed files with 10 additions and 2 deletions
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12
target/riscv/insn_trans/trans_rvv.c.inc
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@ -2128,8 +2128,16 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
s1 = get_gpr(s, a->rs1, EXT_SIGN); s1 = get_gpr(s, a->rs1, EXT_SIGN);
if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd), if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
MAXSZ(s), MAXSZ(s), s1); TCGv_i64 s1_i64 = tcg_temp_new_i64();
tcg_gen_ext_tl_i64(s1_i64, s1);
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), s1_i64);
tcg_temp_free_i64(s1_i64);
} else {
tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), s1);
}
} else { } else {
TCGv_i32 desc; TCGv_i32 desc;
TCGv_i64 s1_i64 = tcg_temp_new_i64(); TCGv_i64 s1_i64 = tcg_temp_new_i64();