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target/mips: Implement hardware page table walker for MIPS32
Implement hardware page table walker. This implementation is limiter only to MIPS32. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Yongbok Kim
Aleksandar Markovic
parent
6301079557
commit
074cfcb4da
@ -537,6 +537,342 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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}
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#endif
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#if !defined(CONFIG_USER_ONLY)
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#if !defined(TARGET_MIPS64)
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/*
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* Perform hardware page table walk
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*
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* Memory accesses are performed using the KERNEL privilege level.
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* Synchronous exceptions detected on memory accesses cause a silent exit
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* from page table walking, resulting in a TLB or XTLB Refill exception.
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*
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* Implementations are not required to support page table walk memory
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* accesses from mapped memory regions. When an unsupported access is
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* attempted, a silent exit is taken, resulting in a TLB or XTLB Refill
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* exception.
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*
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* Note that if an exception is caused by AddressTranslation or LoadMemory
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* functions, the exception is not taken, a silent exit is taken,
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* resulting in a TLB or XTLB Refill exception.
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*/
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static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size,
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uint64_t *pte)
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{
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if ((vaddr & ((entry_size >> 3) - 1)) != 0) {
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return false;
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}
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if (entry_size == 64) {
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*pte = cpu_ldq_code(env, vaddr);
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} else {
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*pte = cpu_ldl_code(env, vaddr);
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}
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return true;
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}
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static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry,
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int entry_size, int ptei)
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{
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uint64_t result = entry;
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uint64_t rixi;
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if (ptei > entry_size) {
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ptei -= 32;
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}
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result >>= (ptei - 2);
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rixi = result & 3;
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result >>= 2;
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result |= rixi << CP0EnLo_XI;
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return result;
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}
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static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
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int directory_index, bool *huge_page, bool *hgpg_directory_hit,
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uint64_t *pw_entrylo0, uint64_t *pw_entrylo1)
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{
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int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1;
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int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F;
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int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
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int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
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int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
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int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
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int directory_shift = (ptew > 1) ? -1 :
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(hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
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int leaf_shift = (ptew > 1) ? -1 :
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(ptew == 1) ? native_shift + 1 : native_shift;
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uint32_t direntry_size = 1 << (directory_shift + 3);
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uint32_t leafentry_size = 1 << (leaf_shift + 3);
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uint64_t entry;
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uint64_t paddr;
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int prot;
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uint64_t lsb = 0;
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uint64_t w = 0;
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if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD,
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ACCESS_INT, cpu_mmu_index(env, false)) !=
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TLBRET_MATCH) {
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/* wrong base address */
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return 0;
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}
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if (!get_pte(env, *vaddr, direntry_size, &entry)) {
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return 0;
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}
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if ((entry & (1 << psn)) && hugepg) {
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*huge_page = true;
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*hgpg_directory_hit = true;
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entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew);
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w = directory_index - 1;
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if (directory_index & 0x1) {
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/* Generate adjacent page from same PTE for odd TLB page */
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lsb = (1 << w) >> 6;
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*pw_entrylo0 = entry & ~lsb; /* even page */
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*pw_entrylo1 = entry | lsb; /* odd page */
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} else if (dph) {
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int oddpagebit = 1 << leaf_shift;
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uint64_t vaddr2 = *vaddr ^ oddpagebit;
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if (*vaddr & oddpagebit) {
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*pw_entrylo1 = entry;
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} else {
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*pw_entrylo0 = entry;
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}
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if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_LOAD,
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ACCESS_INT, cpu_mmu_index(env, false)) !=
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TLBRET_MATCH) {
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return 0;
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}
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if (!get_pte(env, vaddr2, leafentry_size, &entry)) {
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return 0;
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}
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entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew);
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if (*vaddr & oddpagebit) {
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*pw_entrylo0 = entry;
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} else {
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*pw_entrylo1 = entry;
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}
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} else {
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return 0;
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}
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return 1;
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} else {
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*vaddr = entry;
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return 2;
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}
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}
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static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, int rw,
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int mmu_idx)
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{
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int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3F;
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int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3F;
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int mdw = (env->CP0_PWSize >> CP0PS_MDW) & 0x3F;
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int ptw = (env->CP0_PWSize >> CP0PS_PTW) & 0x3F;
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int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
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/* Initial values */
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bool huge_page = false;
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bool hgpg_bdhit = false;
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bool hgpg_gdhit = false;
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bool hgpg_udhit = false;
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bool hgpg_mdhit = false;
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int32_t pw_pagemask = 0;
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target_ulong pw_entryhi = 0;
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uint64_t pw_entrylo0 = 0;
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uint64_t pw_entrylo1 = 0;
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/* Native pointer size */
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/*For the 32-bit architectures, this bit is fixed to 0.*/
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int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
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/* Indices from PWField */
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int pf_gdw = (env->CP0_PWField >> CP0PF_GDW) & 0x3F;
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int pf_udw = (env->CP0_PWField >> CP0PF_UDW) & 0x3F;
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int pf_mdw = (env->CP0_PWField >> CP0PF_MDW) & 0x3F;
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int pf_ptw = (env->CP0_PWField >> CP0PF_PTW) & 0x3F;
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int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
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/* Indices computed from faulting address */
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int gindex = (address >> pf_gdw) & ((1 << gdw) - 1);
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int uindex = (address >> pf_udw) & ((1 << udw) - 1);
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int mindex = (address >> pf_mdw) & ((1 << mdw) - 1);
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int ptindex = (address >> pf_ptw) & ((1 << ptw) - 1);
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/* Other HTW configs */
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int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
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/* HTW Shift values (depend on entry size) */
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int directory_shift = (ptew > 1) ? -1 :
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(hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
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int leaf_shift = (ptew > 1) ? -1 :
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(ptew == 1) ? native_shift + 1 : native_shift;
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/* Offsets into tables */
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int goffset = gindex << directory_shift;
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int uoffset = uindex << directory_shift;
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int moffset = mindex << directory_shift;
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int ptoffset0 = (ptindex >> 1) << (leaf_shift + 1);
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int ptoffset1 = ptoffset0 | (1 << (leaf_shift));
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uint32_t leafentry_size = 1 << (leaf_shift + 3);
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/* Starting address - Page Table Base */
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uint64_t vaddr = env->CP0_PWBase;
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uint64_t dir_entry;
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uint64_t paddr;
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int prot;
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int m;
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if (!(env->CP0_Config3 & (1 << CP0C3_PW))) {
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/* walker is unimplemented */
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return false;
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}
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if (!(env->CP0_PWCtl & (1 << CP0PC_PWEN))) {
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/* walker is disabled */
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return false;
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}
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if (!(gdw > 0 || udw > 0 || mdw > 0)) {
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/* no structure to walk */
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return false;
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}
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if ((directory_shift == -1) || (leaf_shift == -1)) {
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return false;
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}
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/* Global Directory */
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if (gdw > 0) {
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vaddr |= goffset;
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switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit,
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&pw_entrylo0, &pw_entrylo1))
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{
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case 0:
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return false;
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case 1:
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goto refill;
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case 2:
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default:
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break;
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}
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}
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/* Upper directory */
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if (udw > 0) {
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vaddr |= uoffset;
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switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit,
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&pw_entrylo0, &pw_entrylo1))
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{
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case 0:
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return false;
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case 1:
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goto refill;
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case 2:
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default:
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break;
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}
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}
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/* Middle directory */
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if (mdw > 0) {
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vaddr |= moffset;
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switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit,
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&pw_entrylo0, &pw_entrylo1))
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{
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case 0:
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return false;
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case 1:
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goto refill;
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case 2:
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default:
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break;
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}
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}
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/* Leaf Level Page Table - First half of PTE pair */
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vaddr |= ptoffset0;
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if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
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ACCESS_INT, cpu_mmu_index(env, false)) !=
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TLBRET_MATCH) {
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return false;
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}
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if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
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return false;
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}
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dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);
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pw_entrylo0 = dir_entry;
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/* Leaf Level Page Table - Second half of PTE pair */
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vaddr |= ptoffset1;
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if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
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ACCESS_INT, cpu_mmu_index(env, false)) !=
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TLBRET_MATCH) {
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return false;
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}
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if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
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return false;
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}
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dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);
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pw_entrylo1 = dir_entry;
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refill:
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m = (1 << pf_ptw) - 1;
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if (huge_page) {
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switch (hgpg_bdhit << 3 | hgpg_gdhit << 2 | hgpg_udhit << 1 |
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hgpg_mdhit)
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{
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case 4:
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m = (1 << pf_gdw) - 1;
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if (pf_gdw & 1) {
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m >>= 1;
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}
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break;
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case 2:
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m = (1 << pf_udw) - 1;
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if (pf_udw & 1) {
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m >>= 1;
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}
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break;
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case 1:
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m = (1 << pf_mdw) - 1;
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if (pf_mdw & 1) {
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m >>= 1;
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}
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break;
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}
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}
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pw_pagemask = m >> 12;
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update_pagemask(env, pw_pagemask << 13, &pw_pagemask);
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pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF);
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{
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target_ulong tmp_entryhi = env->CP0_EntryHi;
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int32_t tmp_pagemask = env->CP0_PageMask;
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uint64_t tmp_entrylo0 = env->CP0_EntryLo0;
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uint64_t tmp_entrylo1 = env->CP0_EntryLo1;
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env->CP0_EntryHi = pw_entryhi;
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env->CP0_PageMask = pw_pagemask;
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env->CP0_EntryLo0 = pw_entrylo0;
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env->CP0_EntryLo1 = pw_entrylo1;
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/*
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* The hardware page walker inserts a page into the TLB in a manner
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* identical to a TLBWR instruction as executed by the software refill
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* handler.
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*/
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r4k_helper_tlbwr(env);
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env->CP0_EntryHi = tmp_entryhi;
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env->CP0_PageMask = tmp_pagemask;
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env->CP0_EntryLo0 = tmp_entrylo0;
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env->CP0_EntryLo1 = tmp_entrylo1;
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}
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return true;
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}
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#endif
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#endif
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int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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int mmu_idx)
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{
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@ -558,8 +894,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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/* data access */
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#if !defined(CONFIG_USER_ONLY)
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/* XXX: put correct access by using cpu_restore_state()
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correctly */
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/* XXX: put correct access by using cpu_restore_state() correctly */
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access_type = ACCESS_INT;
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ret = get_physical_address(env, &physical, &prot,
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address, rw, access_type, mmu_idx);
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@ -583,6 +918,32 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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} else if (ret < 0)
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#endif
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{
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#if !defined(CONFIG_USER_ONLY)
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#if !defined(TARGET_MIPS64)
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if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
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/*
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* Memory reads during hardware page table walking are performed
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* as if they were kernel-mode load instructions.
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*/
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int mode = (env->hflags & MIPS_HFLAG_KSU);
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bool ret_walker;
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env->hflags &= ~MIPS_HFLAG_KSU;
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ret_walker = page_table_walk_refill(env, address, rw, mmu_idx);
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env->hflags |= mode;
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if (ret_walker) {
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ret = get_physical_address(env, &physical, &prot,
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address, rw, access_type, mmu_idx);
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if (ret == TLBRET_MATCH) {
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tlb_set_page(cs, address & TARGET_PAGE_MASK,
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physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
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mmu_idx, TARGET_PAGE_SIZE);
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ret = 0;
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return ret;
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}
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}
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}
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#endif
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#endif
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raise_mmu_exception(env, address, rw, ret);
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ret = 1;
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}
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@ -211,6 +211,7 @@ uint64_t float_class_d(uint64_t arg, float_status *fst);
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extern unsigned int ieee_rm[];
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int ieee_ex_to_mips(int xcpt);
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void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
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static inline void restore_rounding_mode(CPUMIPSState *env)
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{
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@ -1400,7 +1400,7 @@ void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
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env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
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}
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void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
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void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
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{
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uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
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if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
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@ -1411,6 +1411,11 @@ void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
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}
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}
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void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
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{
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update_pagemask(env, arg1, &env->CP0_PageMask);
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}
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void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
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{
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/* SmartMIPS not implemented */
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