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Revert workaround for -nographic segfault.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2995 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -42,7 +42,6 @@
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#define ENVP_NB_ENTRIES 16
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#define ENVP_ENTRY_SIZE 256
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extern int nographic;
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extern FILE *logfile;
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typedef struct {
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@ -67,18 +66,16 @@ static void malta_fpga_update_display(void *opaque)
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int i;
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MaltaFPGAState *s = opaque;
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if (!nographic) {
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for (i = 7 ; i >= 0 ; i--) {
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if (s->leds & (1 << i))
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leds_text[i] = '#';
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else
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leds_text[i] = ' ';
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}
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leds_text[8] = '\0';
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qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
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qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
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for (i = 7 ; i >= 0 ; i--) {
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if (s->leds & (1 << i))
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leds_text[i] = '#';
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else
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leds_text[i] = ' ';
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}
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leds_text[8] = '\0';
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qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
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qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
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}
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/*
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@ -415,22 +412,20 @@ MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
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cpu_register_physical_memory(base, 0x900, malta);
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cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
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if (!nographic) {
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s->display = qemu_chr_open("vc");
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qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "+ +\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "\n");
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qemu_chr_printf(s->display, "Malta ASCII\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "+ +\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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s->display = qemu_chr_open("vc");
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qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "+ +\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "\n");
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qemu_chr_printf(s->display, "Malta ASCII\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "+ +\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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uart_chr = qemu_chr_open("vc");
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qemu_chr_printf(uart_chr, "CBUS UART\r\n");
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s->uart = serial_mm_init(base + 0x900, 3, env->irq[2], uart_chr, 1);
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}
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uart_chr = qemu_chr_open("vc");
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qemu_chr_printf(uart_chr, "CBUS UART\r\n");
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s->uart = serial_mm_init(base + 0x900, 3, env->irq[2], uart_chr, 1);
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malta_fpga_reset(s);
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qemu_register_reset(malta_fpga_reset, s);
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