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x3130/downstream: support aer.

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add aer support.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Isaku Yamahata 2010-11-16 17:26:12 +09:00 committed by Michael S. Tsirkin
parent a158f92fa7
commit 09b926d446
1 changed files with 33 additions and 10 deletions
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43
hw/xio3130_downstream.c
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@ -42,7 +42,7 @@ static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
pcie_cap_flr_write_config(d, address, val, len); pcie_cap_flr_write_config(d, address, val, len);
pcie_cap_slot_write_config(d, address, val, len); pcie_cap_slot_write_config(d, address, val, len);
msi_write_config(d, address, val, len); msi_write_config(d, address, val, len);
/* TODO: AER */ pcie_aer_write_config(d, address, val, len);
} }
static void xio3130_downstream_reset(DeviceState *qdev) static void xio3130_downstream_reset(DeviceState *qdev)
@ -61,6 +61,7 @@ static int xio3130_downstream_initfn(PCIDevice *d)
PCIEPort *p = DO_UPCAST(PCIEPort, br, br); PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
PCIESlot *s = DO_UPCAST(PCIESlot, port, p); PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
int rc; int rc;
int tmp;
rc = pci_bridge_initfn(d); rc = pci_bridge_initfn(d);
if (rc < 0) { if (rc < 0) {
@ -76,17 +77,17 @@ static int xio3130_downstream_initfn(PCIDevice *d)
XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
if (rc < 0) { if (rc < 0) {
return rc; goto err_bridge;
} }
rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
if (rc < 0) { if (rc < 0) {
return rc; goto err_bridge;
} }
rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
p->port); p->port);
if (rc < 0) { if (rc < 0) {
return rc; goto err_msi;
} }
pcie_cap_flr_init(d); /* TODO: implement FLR */ pcie_cap_flr_init(d); /* TODO: implement FLR */
pcie_cap_deverr_init(d); pcie_cap_deverr_init(d);
@ -94,19 +95,38 @@ static int xio3130_downstream_initfn(PCIDevice *d)
pcie_chassis_create(s->chassis); pcie_chassis_create(s->chassis);
rc = pcie_chassis_add_slot(s); rc = pcie_chassis_add_slot(s);
if (rc < 0) { if (rc < 0) {
return rc; goto err_pcie_cap;
} }
pcie_cap_ari_init(d); pcie_cap_ari_init(d);
/* TODO: AER */ rc = pcie_aer_init(d, XIO3130_AER_OFFSET);
if (rc < 0) {
goto err;
}
return 0; return 0;
err:
pcie_chassis_del_slot(s);
err_pcie_cap:
pcie_cap_exit(d);
err_msi:
msi_uninit(d);
err_bridge:
tmp = pci_bridge_exitfn(d);
assert(!tmp);
return rc;
} }
static int xio3130_downstream_exitfn(PCIDevice *d) static int xio3130_downstream_exitfn(PCIDevice *d)
{ {
/* TODO: AER */ PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
msi_uninit(d); PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
pcie_aer_exit(d);
pcie_chassis_del_slot(s);
pcie_cap_exit(d); pcie_cap_exit(d);
msi_uninit(d);
return pci_bridge_exitfn(d); return pci_bridge_exitfn(d);
} }
@ -144,7 +164,8 @@ static const VMStateDescription vmstate_xio3130_downstream = {
.post_load = pcie_cap_slot_post_load, .post_load = pcie_cap_slot_post_load,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
/* TODO: AER */ VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
vmstate_pcie_aer_log, PCIEAERLog),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
@ -166,7 +187,9 @@ static PCIDeviceInfo xio3130_downstream_info = {
DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
/* TODO: AER */ DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
port.br.dev.exp.aer_log.log_max,
PCIE_AER_LOG_MAX_DEFAULT),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
} }
}; };