xemu-project/xemu
1
0
Fork 0
mirror of https://github.com/xemu-project/xemu.git synced 2024-11-24 03:59:52 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

target-tilegx: Implement v*shl, v*shru, and v*shrs instructions

Browse Source 
v2sh* are implemented with helper functions; v4sh* are implmeneted
with inline code.

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1442872055-2836-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Chen Gang 2015-09-22 05:47:35 +08:00 committed by Richard Henderson
parent 0551301076
commit 0ab0a3d768
3 changed files with 73 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
target-tilegx/helper.h
View File

@ -8,3 +8,6 @@ DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v2shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v2shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v2shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)

31
target-tilegx/simd_helper.c
View File

@ -25,6 +25,7 @@
/* Broadcast a value to all elements of a vector. */
#define V1(X) (((X) & 0xff) * 0x0101010101010101ull)
#define V2(X) (((X) & 0xffff) * 0x0001000100010001ull)
uint64_t helper_v1shl(uint64_t a, uint64_t b)
@ -36,6 +37,15 @@ uint64_t helper_v1shl(uint64_t a, uint64_t b)
return (a & m) << b;
}
uint64_t helper_v2shl(uint64_t a, uint64_t b)
{
uint64_t m;
b &= 15;
m = V2(0xffff >> b);
return (a & m) << b;
}
uint64_t helper_v1shru(uint64_t a, uint64_t b)
{
uint64_t m;
@ -45,6 +55,15 @@ uint64_t helper_v1shru(uint64_t a, uint64_t b)
return (a & m) >> b;
}
uint64_t helper_v2shru(uint64_t a, uint64_t b)
{
uint64_t m;
b &= 15;
m = V2(0xffff << b);
return (a & m) >> b;
}
uint64_t helper_v1shrs(uint64_t a, uint64_t b)
{
uint64_t r = 0;
@ -56,3 +75,15 @@ uint64_t helper_v1shrs(uint64_t a, uint64_t b)
}
return r;
}
uint64_t helper_v2shrs(uint64_t a, uint64_t b)
{
uint64_t r = 0;
int i;
b &= 15;
for (i = 0; i < 64; i += 16) {
r = deposit64(r, i, 16, sextract64(a, i + b, 16 - b));
}
return r;
}

39
target-tilegx/translate.c
View File

@ -339,6 +339,25 @@ static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb
return TILEGX_EXCP_NONE;
}
static void gen_v4sh(TCGv d64, TCGv a64, TCGv b64,
void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32))
{
TCGv_i32 al = tcg_temp_new_i32();
TCGv_i32 ah = tcg_temp_new_i32();
TCGv_i32 bl = tcg_temp_new_i32();
tcg_gen_extr_i64_i32(al, ah, a64);
tcg_gen_extrl_i64_i32(bl, b64);
tcg_gen_andi_i32(bl, bl, 31);
generate(al, al, bl);
generate(ah, ah, bl);
tcg_gen_concat_i32_i64(d64, al, ah);
tcg_temp_free_i32(al);
tcg_temp_free_i32(ah);
tcg_temp_free_i32(bl);
}
static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca)
{
@ -1144,12 +1163,22 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(V2SADU, 0, X0):
case OE_RRR(V2SHLSC, 0, X0):
case OE_RRR(V2SHLSC, 0, X1):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V2SHL, 0, X0):
case OE_RRR(V2SHL, 0, X1):
gen_helper_v2shl(tdest, tsrca, tsrcb);
mnemonic = "v2shl";
break;
case OE_RRR(V2SHRS, 0, X0):
case OE_RRR(V2SHRS, 0, X1):
gen_helper_v2shrs(tdest, tsrca, tsrcb);
mnemonic = "v2shrs";
break;
case OE_RRR(V2SHRU, 0, X0):
case OE_RRR(V2SHRU, 0, X1):
gen_helper_v2shru(tdest, tsrca, tsrcb);
mnemonic = "v2shru";
break;
case OE_RRR(V2SUBSC, 0, X0):
case OE_RRR(V2SUBSC, 0, X1):
case OE_RRR(V2SUB, 0, X0):
@ -1174,12 +1203,22 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(V4PACKSC, 0, X1):
case OE_RRR(V4SHLSC, 0, X0):
case OE_RRR(V4SHLSC, 0, X1):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V4SHL, 0, X0):
case OE_RRR(V4SHL, 0, X1):
gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shl_i32);
mnemonic = "v4shl";
break;
case OE_RRR(V4SHRS, 0, X0):
case OE_RRR(V4SHRS, 0, X1):
gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_sar_i32);
mnemonic = "v4shrs";
break;
case OE_RRR(V4SHRU, 0, X0):
case OE_RRR(V4SHRU, 0, X1):
gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shr_i32);
mnemonic = "v4shru";
break;
case OE_RRR(V4SUBSC, 0, X0):
case OE_RRR(V4SUBSC, 0, X1):
case OE_RRR(V4SUB, 0, X0):