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hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)
This patch realize the PCH-PIC interrupt controller. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-33-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Xiaojuan Yang
Richard Henderson
parent
f6783e3438
commit
0f4fcf1845
@ -1135,6 +1135,7 @@ F: hw/loongarch/
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F: include/hw/loongarch/virt.h
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F: include/hw/loongarch/virt.h
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F: include/hw/intc/loongarch_*.h
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F: include/hw/intc/loongarch_*.h
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F: hw/intc/loongarch_*.c
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F: hw/intc/loongarch_*.c
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F: include/hw/pci-host/ls7a.h
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M68K Machines
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M68K Machines
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-------------
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-------------
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@ -90,3 +90,7 @@ config NIOS2_VIC
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config LOONGARCH_IPI
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config LOONGARCH_IPI
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bool
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bool
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config LOONGARCH_PCH_PIC
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bool
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select UNIMP
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431
hw/intc/loongarch_pch_pic.c
Normal file
431
hw/intc/loongarch_pch_pic.c
Normal file
@ -0,0 +1,431 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* QEMU Loongson 7A1000 I/O interrupt controller.
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*
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* Copyright (C) 2021 Loongson Technology Corporation Limited
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/loongarch/virt.h"
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#include "hw/irq.h"
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#include "hw/intc/loongarch_pch_pic.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
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{
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unsigned long val;
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int irq;
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if (level) {
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val = mask & s->intirr & ~s->int_mask;
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if (val) {
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irq = find_first_bit(&val, 64);
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s->intisr |= 0x1ULL << irq;
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qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 1);
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}
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} else {
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val = mask & s->intisr;
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if (val) {
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irq = find_first_bit(&val, 64);
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s->intisr &= ~(0x1ULL << irq);
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qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 0);
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}
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}
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}
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static void pch_pic_irq_handler(void *opaque, int irq, int level)
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{
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LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
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uint64_t mask = 1ULL << irq;
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assert(irq < PCH_PIC_IRQ_NUM);
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trace_loongarch_pch_pic_irq_handler(irq, level);
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if (s->intedge & mask) {
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/* Edge triggered */
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if (level) {
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if ((s->last_intirr & mask) == 0) {
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s->intirr |= mask;
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}
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s->last_intirr |= mask;
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} else {
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s->last_intirr &= ~mask;
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}
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} else {
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/* Level triggered */
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if (level) {
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s->intirr |= mask;
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s->last_intirr |= mask;
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} else {
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s->intirr &= ~mask;
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s->last_intirr &= ~mask;
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}
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}
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pch_pic_update_irq(s, mask, level);
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}
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static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,
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unsigned size)
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{
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LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
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uint64_t val = 0;
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uint32_t offset = addr & 0xfff;
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switch (offset) {
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case PCH_PIC_INT_ID_LO:
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val = PCH_PIC_INT_ID_VAL;
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break;
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case PCH_PIC_INT_ID_HI:
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val = PCH_PIC_INT_ID_NUM;
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break;
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case PCH_PIC_INT_MASK_LO:
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val = (uint32_t)s->int_mask;
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break;
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case PCH_PIC_INT_MASK_HI:
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val = s->int_mask >> 32;
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break;
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case PCH_PIC_INT_EDGE_LO:
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val = (uint32_t)s->intedge;
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break;
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case PCH_PIC_INT_EDGE_HI:
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val = s->intedge >> 32;
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break;
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case PCH_PIC_HTMSI_EN_LO:
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val = (uint32_t)s->htmsi_en;
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break;
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case PCH_PIC_HTMSI_EN_HI:
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val = s->htmsi_en >> 32;
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break;
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case PCH_PIC_AUTO_CTRL0_LO:
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case PCH_PIC_AUTO_CTRL0_HI:
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case PCH_PIC_AUTO_CTRL1_LO:
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case PCH_PIC_AUTO_CTRL1_HI:
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break;
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default:
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break;
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}
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trace_loongarch_pch_pic_low_readw(size, addr, val);
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return val;
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}
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static uint64_t get_writew_val(uint64_t value, uint32_t target, bool hi)
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{
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uint64_t mask = 0xffffffff00000000;
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uint64_t data = target;
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return hi ? (value & ~mask) | (data << 32) : (value & mask) | data;
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}
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static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
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uint32_t offset, old_valid, data = (uint32_t)value;
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uint64_t old, int_mask;
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offset = addr & 0xfff;
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trace_loongarch_pch_pic_low_writew(size, addr, data);
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switch (offset) {
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case PCH_PIC_INT_MASK_LO:
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old = s->int_mask;
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s->int_mask = get_writew_val(old, data, 0);
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old_valid = (uint32_t)old;
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if (old_valid & ~data) {
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pch_pic_update_irq(s, (old_valid & ~data), 1);
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}
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if (~old_valid & data) {
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pch_pic_update_irq(s, (~old_valid & data), 0);
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}
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break;
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case PCH_PIC_INT_MASK_HI:
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old = s->int_mask;
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s->int_mask = get_writew_val(old, data, 1);
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old_valid = (uint32_t)(old >> 32);
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int_mask = old_valid & ~data;
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if (int_mask) {
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pch_pic_update_irq(s, int_mask << 32, 1);
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}
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int_mask = ~old_valid & data;
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if (int_mask) {
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pch_pic_update_irq(s, int_mask << 32, 0);
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}
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break;
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case PCH_PIC_INT_EDGE_LO:
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s->intedge = get_writew_val(s->intedge, data, 0);
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break;
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case PCH_PIC_INT_EDGE_HI:
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s->intedge = get_writew_val(s->intedge, data, 1);
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break;
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case PCH_PIC_INT_CLEAR_LO:
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if (s->intedge & data) {
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s->intirr &= (~data);
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pch_pic_update_irq(s, data, 0);
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s->intisr &= (~data);
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}
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break;
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case PCH_PIC_INT_CLEAR_HI:
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value <<= 32;
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if (s->intedge & value) {
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s->intirr &= (~value);
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pch_pic_update_irq(s, value, 0);
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s->intisr &= (~value);
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}
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break;
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case PCH_PIC_HTMSI_EN_LO:
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s->htmsi_en = get_writew_val(s->htmsi_en, data, 0);
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break;
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case PCH_PIC_HTMSI_EN_HI:
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s->htmsi_en = get_writew_val(s->htmsi_en, data, 1);
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break;
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case PCH_PIC_AUTO_CTRL0_LO:
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case PCH_PIC_AUTO_CTRL0_HI:
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case PCH_PIC_AUTO_CTRL1_LO:
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case PCH_PIC_AUTO_CTRL1_HI:
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break;
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default:
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break;
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}
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}
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static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
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unsigned size)
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{
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LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
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uint64_t val = 0;
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uint32_t offset = addr & 0xfff;
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switch (offset) {
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case STATUS_LO_START:
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val = (uint32_t)(s->intisr & (~s->int_mask));
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break;
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case STATUS_HI_START:
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val = (s->intisr & (~s->int_mask)) >> 32;
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break;
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case POL_LO_START:
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val = (uint32_t)s->int_polarity;
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break;
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case POL_HI_START:
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val = s->int_polarity >> 32;
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break;
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default:
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break;
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}
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trace_loongarch_pch_pic_high_readw(size, addr, val);
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return val;
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}
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static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
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uint32_t offset, data = (uint32_t)value;
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offset = addr & 0xfff;
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trace_loongarch_pch_pic_high_writew(size, addr, data);
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switch (offset) {
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case STATUS_LO_START:
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s->intisr = get_writew_val(s->intisr, data, 0);
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break;
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case STATUS_HI_START:
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s->intisr = get_writew_val(s->intisr, data, 1);
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break;
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case POL_LO_START:
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s->int_polarity = get_writew_val(s->int_polarity, data, 0);
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break;
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case POL_HI_START:
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s->int_polarity = get_writew_val(s->int_polarity, data, 1);
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break;
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default:
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break;
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}
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}
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static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
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unsigned size)
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{
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LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
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uint64_t val = 0;
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uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
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int64_t offset_tmp;
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switch (offset) {
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case PCH_PIC_HTMSI_VEC_OFFSET ... PCH_PIC_HTMSI_VEC_END:
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offset_tmp = offset - PCH_PIC_HTMSI_VEC_OFFSET;
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if (offset_tmp >= 0 && offset_tmp < 64) {
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val = s->htmsi_vector[offset_tmp];
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}
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break;
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case PCH_PIC_ROUTE_ENTRY_OFFSET ... PCH_PIC_ROUTE_ENTRY_END:
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offset_tmp = offset - PCH_PIC_ROUTE_ENTRY_OFFSET;
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if (offset_tmp >= 0 && offset_tmp < 64) {
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val = s->route_entry[offset_tmp];
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}
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break;
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default:
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break;
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}
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trace_loongarch_pch_pic_readb(size, addr, val);
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return val;
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}
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static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
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int32_t offset_tmp;
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uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
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trace_loongarch_pch_pic_writeb(size, addr, data);
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switch (offset) {
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case PCH_PIC_HTMSI_VEC_OFFSET ... PCH_PIC_HTMSI_VEC_END:
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offset_tmp = offset - PCH_PIC_HTMSI_VEC_OFFSET;
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if (offset_tmp >= 0 && offset_tmp < 64) {
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s->htmsi_vector[offset_tmp] = (uint8_t)(data & 0xff);
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}
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break;
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case PCH_PIC_ROUTE_ENTRY_OFFSET ... PCH_PIC_ROUTE_ENTRY_END:
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offset_tmp = offset - PCH_PIC_ROUTE_ENTRY_OFFSET;
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if (offset_tmp >= 0 && offset_tmp < 64) {
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s->route_entry[offset_tmp] = (uint8_t)(data & 0xff);
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}
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break;
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default:
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break;
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}
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}
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static const MemoryRegionOps loongarch_pch_pic_reg32_low_ops = {
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.read = loongarch_pch_pic_low_readw,
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.write = loongarch_pch_pic_low_writew,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static const MemoryRegionOps loongarch_pch_pic_reg32_high_ops = {
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.read = loongarch_pch_pic_high_readw,
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.write = loongarch_pch_pic_high_writew,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static const MemoryRegionOps loongarch_pch_pic_reg8_ops = {
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.read = loongarch_pch_pic_readb,
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.write = loongarch_pch_pic_writeb,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
|
||||||
|
.impl = {
|
||||||
|
.min_access_size = 1,
|
||||||
|
.max_access_size = 1,
|
||||||
|
},
|
||||||
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void loongarch_pch_pic_reset(DeviceState *d)
|
||||||
|
{
|
||||||
|
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(d);
|
||||||
|
int i;
|
||||||
|
|
||||||
|
s->int_mask = -1;
|
||||||
|
s->htmsi_en = 0x0;
|
||||||
|
s->intedge = 0x0;
|
||||||
|
s->intclr = 0x0;
|
||||||
|
s->auto_crtl0 = 0x0;
|
||||||
|
s->auto_crtl1 = 0x0;
|
||||||
|
for (i = 0; i < 64; i++) {
|
||||||
|
s->route_entry[i] = 0x1;
|
||||||
|
s->htmsi_vector[i] = 0x0;
|
||||||
|
}
|
||||||
|
s->intirr = 0x0;
|
||||||
|
s->intisr = 0x0;
|
||||||
|
s->last_intirr = 0x0;
|
||||||
|
s->int_polarity = 0x0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void loongarch_pch_pic_init(Object *obj)
|
||||||
|
{
|
||||||
|
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj);
|
||||||
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
||||||
|
|
||||||
|
memory_region_init_io(&s->iomem32_low, obj,
|
||||||
|
&loongarch_pch_pic_reg32_low_ops,
|
||||||
|
s, PCH_PIC_NAME(.reg32_part1), 0x100);
|
||||||
|
memory_region_init_io(&s->iomem8, obj, &loongarch_pch_pic_reg8_ops,
|
||||||
|
s, PCH_PIC_NAME(.reg8), 0x2a0);
|
||||||
|
memory_region_init_io(&s->iomem32_high, obj,
|
||||||
|
&loongarch_pch_pic_reg32_high_ops,
|
||||||
|
s, PCH_PIC_NAME(.reg32_part2), 0xc60);
|
||||||
|
sysbus_init_mmio(sbd, &s->iomem32_low);
|
||||||
|
sysbus_init_mmio(sbd, &s->iomem8);
|
||||||
|
sysbus_init_mmio(sbd, &s->iomem32_high);
|
||||||
|
|
||||||
|
qdev_init_gpio_out(DEVICE(obj), s->parent_irq, PCH_PIC_IRQ_NUM);
|
||||||
|
qdev_init_gpio_in(DEVICE(obj), pch_pic_irq_handler, PCH_PIC_IRQ_NUM);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const VMStateDescription vmstate_loongarch_pch_pic = {
|
||||||
|
.name = TYPE_LOONGARCH_PCH_PIC,
|
||||||
|
.version_id = 1,
|
||||||
|
.minimum_version_id = 1,
|
||||||
|
.fields = (VMStateField[]) {
|
||||||
|
VMSTATE_UINT64(int_mask, LoongArchPCHPIC),
|
||||||
|
VMSTATE_UINT64(htmsi_en, LoongArchPCHPIC),
|
||||||
|
VMSTATE_UINT64(intedge, LoongArchPCHPIC),
|
||||||
|
VMSTATE_UINT64(intclr, LoongArchPCHPIC),
|
||||||
|
VMSTATE_UINT64(auto_crtl0, LoongArchPCHPIC),
|
||||||
|
VMSTATE_UINT64(auto_crtl1, LoongArchPCHPIC),
|
||||||
|
VMSTATE_UINT8_ARRAY(route_entry, LoongArchPCHPIC, 64),
|
||||||
|
VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPCHPIC, 64),
|
||||||
|
VMSTATE_UINT64(last_intirr, LoongArchPCHPIC),
|
||||||
|
VMSTATE_UINT64(intirr, LoongArchPCHPIC),
|
||||||
|
VMSTATE_UINT64(intisr, LoongArchPCHPIC),
|
||||||
|
VMSTATE_UINT64(int_polarity, LoongArchPCHPIC),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
|
||||||
|
{
|
||||||
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||||
|
|
||||||
|
dc->reset = loongarch_pch_pic_reset;
|
||||||
|
dc->vmsd = &vmstate_loongarch_pch_pic;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const TypeInfo loongarch_pch_pic_info = {
|
||||||
|
.name = TYPE_LOONGARCH_PCH_PIC,
|
||||||
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||||||
|
.instance_size = sizeof(LoongArchPCHPIC),
|
||||||
|
.instance_init = loongarch_pch_pic_init,
|
||||||
|
.class_init = loongarch_pch_pic_class_init,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void loongarch_pch_pic_register_types(void)
|
||||||
|
{
|
||||||
|
type_register_static(&loongarch_pch_pic_info);
|
||||||
|
}
|
||||||
|
|
||||||
|
type_init(loongarch_pch_pic_register_types)
|
||||||
@ -64,3 +64,4 @@ specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c'))
|
|||||||
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
|
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
|
||||||
specific_ss.add(when: 'CONFIG_NIOS2_VIC', if_true: files('nios2_vic.c'))
|
specific_ss.add(when: 'CONFIG_NIOS2_VIC', if_true: files('nios2_vic.c'))
|
||||||
specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
|
specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
|
||||||
|
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
|
||||||
|
|||||||
@ -291,3 +291,12 @@ sh_intc_set(int id, int enable) "setting interrupt group %d to %d"
|
|||||||
# loongarch_ipi.c
|
# loongarch_ipi.c
|
||||||
loongarch_ipi_read(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
|
loongarch_ipi_read(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
|
||||||
loongarch_ipi_write(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
|
loongarch_ipi_write(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
|
||||||
|
|
||||||
|
# loongarch_pch_pic.c
|
||||||
|
loongarch_pch_pic_irq_handler(int irq, int level) "irq %d level %d"
|
||||||
|
loongarch_pch_pic_low_readw(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64
|
||||||
|
loongarch_pch_pic_low_writew(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64
|
||||||
|
loongarch_pch_pic_high_readw(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64
|
||||||
|
loongarch_pch_pic_high_writew(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64
|
||||||
|
loongarch_pch_pic_readb(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64
|
||||||
|
loongarch_pch_pic_writeb(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64
|
||||||
|
|||||||
@ -3,3 +3,4 @@ config LOONGARCH_VIRT
|
|||||||
select PCI
|
select PCI
|
||||||
select PCI_EXPRESS_GENERIC_BRIDGE
|
select PCI_EXPRESS_GENERIC_BRIDGE
|
||||||
select LOONGARCH_IPI
|
select LOONGARCH_IPI
|
||||||
|
select LOONGARCH_PCH_PIC
|
||||||
|
|||||||
69
include/hw/intc/loongarch_pch_pic.h
Normal file
69
include/hw/intc/loongarch_pch_pic.h
Normal file
@ -0,0 +1,69 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||||
|
/*
|
||||||
|
* LoongArch 7A1000 I/O interrupt controller definitions
|
||||||
|
*
|
||||||
|
* Copyright (c) 2021 Loongson Technology Corporation Limited
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
|
||||||
|
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
|
||||||
|
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
|
||||||
|
|
||||||
|
#define PCH_PIC_IRQ_START 0
|
||||||
|
#define PCH_PIC_IRQ_END 63
|
||||||
|
#define PCH_PIC_IRQ_NUM 64
|
||||||
|
#define PCH_PIC_INT_ID_VAL 0x7000000UL
|
||||||
|
#define PCH_PIC_INT_ID_NUM 0x3f0001UL
|
||||||
|
|
||||||
|
#define PCH_PIC_INT_ID_LO 0x00
|
||||||
|
#define PCH_PIC_INT_ID_HI 0x04
|
||||||
|
#define PCH_PIC_INT_MASK_LO 0x20
|
||||||
|
#define PCH_PIC_INT_MASK_HI 0x24
|
||||||
|
#define PCH_PIC_HTMSI_EN_LO 0x40
|
||||||
|
#define PCH_PIC_HTMSI_EN_HI 0x44
|
||||||
|
#define PCH_PIC_INT_EDGE_LO 0x60
|
||||||
|
#define PCH_PIC_INT_EDGE_HI 0x64
|
||||||
|
#define PCH_PIC_INT_CLEAR_LO 0x80
|
||||||
|
#define PCH_PIC_INT_CLEAR_HI 0x84
|
||||||
|
#define PCH_PIC_AUTO_CTRL0_LO 0xc0
|
||||||
|
#define PCH_PIC_AUTO_CTRL0_HI 0xc4
|
||||||
|
#define PCH_PIC_AUTO_CTRL1_LO 0xe0
|
||||||
|
#define PCH_PIC_AUTO_CTRL1_HI 0xe4
|
||||||
|
#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
|
||||||
|
#define PCH_PIC_ROUTE_ENTRY_END 0x13f
|
||||||
|
#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
|
||||||
|
#define PCH_PIC_HTMSI_VEC_END 0x23f
|
||||||
|
#define PCH_PIC_INT_STATUS_LO 0x3a0
|
||||||
|
#define PCH_PIC_INT_STATUS_HI 0x3a4
|
||||||
|
#define PCH_PIC_INT_POL_LO 0x3e0
|
||||||
|
#define PCH_PIC_INT_POL_HI 0x3e4
|
||||||
|
|
||||||
|
#define STATUS_LO_START 0
|
||||||
|
#define STATUS_HI_START 0x4
|
||||||
|
#define POL_LO_START 0x40
|
||||||
|
#define POL_HI_START 0x44
|
||||||
|
struct LoongArchPCHPIC {
|
||||||
|
SysBusDevice parent_obj;
|
||||||
|
qemu_irq parent_irq[64];
|
||||||
|
uint64_t int_mask; /*0x020 interrupt mask register*/
|
||||||
|
uint64_t htmsi_en; /*0x040 1=msi*/
|
||||||
|
uint64_t intedge; /*0x060 edge=1 level =0*/
|
||||||
|
uint64_t intclr; /*0x080 for clean edge int,set 1 clean,set 0 is noused*/
|
||||||
|
uint64_t auto_crtl0; /*0x0c0*/
|
||||||
|
uint64_t auto_crtl1; /*0x0e0*/
|
||||||
|
uint64_t last_intirr; /* edge detection */
|
||||||
|
uint64_t intirr; /* 0x380 interrupt request register */
|
||||||
|
uint64_t intisr; /* 0x3a0 interrupt service register */
|
||||||
|
/*
|
||||||
|
* 0x3e0 interrupt level polarity selection
|
||||||
|
* register 0 for high level trigger
|
||||||
|
*/
|
||||||
|
uint64_t int_polarity;
|
||||||
|
|
||||||
|
uint8_t route_entry[64]; /*0x100 - 0x138*/
|
||||||
|
uint8_t htmsi_vector[64]; /*0x200 - 0x238*/
|
||||||
|
|
||||||
|
MemoryRegion iomem32_low;
|
||||||
|
MemoryRegion iomem32_high;
|
||||||
|
MemoryRegion iomem8;
|
||||||
|
};
|
||||||
30
include/hw/pci-host/ls7a.h
Normal file
30
include/hw/pci-host/ls7a.h
Normal file
@ -0,0 +1,30 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||||
|
/*
|
||||||
|
* QEMU LoongArch CPU
|
||||||
|
*
|
||||||
|
* Copyright (c) 2021 Loongson Technology Corporation Limited
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef HW_LS7A_H
|
||||||
|
#define HW_LS7A_H
|
||||||
|
|
||||||
|
#include "hw/pci/pci.h"
|
||||||
|
#include "hw/pci/pcie_host.h"
|
||||||
|
#include "hw/pci-host/pam.h"
|
||||||
|
#include "qemu/units.h"
|
||||||
|
#include "qemu/range.h"
|
||||||
|
#include "qom/object.h"
|
||||||
|
|
||||||
|
#define LS7A_PCH_REG_BASE 0x10000000UL
|
||||||
|
#define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE)
|
||||||
|
#define LS7A_PCH_MSI_ADDR_LOW 0x2FF00000UL
|
||||||
|
|
||||||
|
/*
|
||||||
|
* According to the kernel pch irq start from 64 offset
|
||||||
|
* 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs
|
||||||
|
* used for pci device.
|
||||||
|
*/
|
||||||
|
#define PCH_PIC_IRQ_OFFSET 64
|
||||||
|
#define LS7A_DEVICE_IRQS 16
|
||||||
|
#define LS7A_PCI_IRQS 48
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue
Block a user