From 3e2a0cb99d26fd5fb34ab8c50f90d4292363245d Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Wed, 6 May 2020 10:25:05 +0200 Subject: [PATCH 01/14] hw/net/xilinx_axienet: Auto-clear PHY Autoneg Auto-clear PHY CR Autoneg bits. This makes this model work with recent Linux kernels. Reviewed-by: Francisco Iglesias Signed-off-by: Edgar E. Iglesias Message-Id: <20200506082513.18751-2-edgar.iglesias@gmail.com> --- hw/net/xilinx_axienet.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 704788811a..0f97510d8a 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -149,8 +149,8 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int data) break; } - /* Unconditionally clear regs[BMCR][BMCR_RESET] */ - phy->regs[0] &= ~0x8000; + /* Unconditionally clear regs[BMCR][BMCR_RESET] and auto-neg */ + phy->regs[0] &= ~0x8200; } static void From 0d9047c4d999add0be60b12f204ce4c14c457415 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Wed, 6 May 2020 10:25:06 +0200 Subject: [PATCH 02/14] hw/net/xilinx_axienet: Cleanup stream->push assignment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Split the shared stream_class_init function to assign stream->push with better type-safety. Reviewed-by: Alistair Francis Reviewed-by: Francisco Iglesias Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200506082513.18751-3-edgar.iglesias@gmail.com> --- hw/net/xilinx_axienet.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 0f97510d8a..84073753d7 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -1029,11 +1029,19 @@ static void xilinx_enet_class_init(ObjectClass *klass, void *data) dc->reset = xilinx_axienet_reset; } -static void xilinx_enet_stream_class_init(ObjectClass *klass, void *data) +static void xilinx_enet_control_stream_class_init(ObjectClass *klass, + void *data) { StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); - ssc->push = data; + ssc->push = xilinx_axienet_control_stream_push; +} + +static void xilinx_enet_data_stream_class_init(ObjectClass *klass, void *data) +{ + StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); + + ssc->push = xilinx_axienet_data_stream_push; } static const TypeInfo xilinx_enet_info = { @@ -1048,8 +1056,7 @@ static const TypeInfo xilinx_enet_data_stream_info = { .name = TYPE_XILINX_AXI_ENET_DATA_STREAM, .parent = TYPE_OBJECT, .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), - .class_init = xilinx_enet_stream_class_init, - .class_data = xilinx_axienet_data_stream_push, + .class_init = xilinx_enet_data_stream_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_STREAM_SLAVE }, { } @@ -1060,8 +1067,7 @@ static const TypeInfo xilinx_enet_control_stream_info = { .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM, .parent = TYPE_OBJECT, .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), - .class_init = xilinx_enet_stream_class_init, - .class_data = xilinx_axienet_control_stream_push, + .class_init = xilinx_enet_control_stream_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_STREAM_SLAVE }, { } From da59e178d743b8fdb44518f2e58590467ba5ec9e Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Wed, 6 May 2020 10:25:07 +0200 Subject: [PATCH 03/14] hw/net/xilinx_axienet: Remove unncessary cast MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove unncessary cast, buf is already uint8_t *. No functional change. Reviewed-by: Alistair Francis Reviewed-by: Francisco Iglesias Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200506082513.18751-4-edgar.iglesias@gmail.com> --- hw/net/xilinx_axienet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 84073753d7..c8dfcda3ee 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -918,7 +918,7 @@ xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size) uint16_t csum; tmp_csum = net_checksum_add(size - start_off, - (uint8_t *)buf + start_off); + buf + start_off); /* Accumulate the seed. */ tmp_csum += s->hdr[2] & 0xffff; From e3a8926d0e91e6783157a9934bd6f59c7efaa992 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Wed, 6 May 2020 10:25:08 +0200 Subject: [PATCH 04/14] hw/dma/xilinx_axidma: Add DMA memory-region property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add DMA memory-region property to externally control what address-space this DMA operates on. Reviewed-by: Alistair Francis Reviewed-by: Francisco Iglesias Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200506082513.18751-5-edgar.iglesias@gmail.com> --- hw/dma/xilinx_axidma.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 018f36991b..4540051448 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -33,6 +33,7 @@ #include "qemu/log.h" #include "qemu/module.h" +#include "sysemu/dma.h" #include "hw/stream.h" #define D(x) @@ -103,6 +104,7 @@ enum { }; struct Stream { + struct XilinxAXIDMA *dma; ptimer_state *ptimer; qemu_irq irq; @@ -125,6 +127,9 @@ struct XilinxAXIDMAStreamSlave { struct XilinxAXIDMA { SysBusDevice busdev; MemoryRegion iomem; + MemoryRegion *dma_mr; + AddressSpace as; + uint32_t freqhz; StreamSlave *tx_data_dev; StreamSlave *tx_control_dev; @@ -186,7 +191,7 @@ static void stream_desc_load(struct Stream *s, hwaddr addr) { struct SDesc *d = &s->desc; - cpu_physical_memory_read(addr, d, sizeof *d); + address_space_read(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, d, sizeof *d); /* Convert from LE into host endianness. */ d->buffer_address = le64_to_cpu(d->buffer_address); @@ -204,7 +209,8 @@ static void stream_desc_store(struct Stream *s, hwaddr addr) d->nxtdesc = cpu_to_le64(d->nxtdesc); d->control = cpu_to_le32(d->control); d->status = cpu_to_le32(d->status); - cpu_physical_memory_write(addr, d, sizeof *d); + address_space_write(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, + d, sizeof *d); } static void stream_update_irq(struct Stream *s) @@ -286,8 +292,9 @@ static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev, txlen + s->pos); } - cpu_physical_memory_read(s->desc.buffer_address, - s->txbuf + s->pos, txlen); + address_space_read(&s->dma->as, s->desc.buffer_address, + MEMTXATTRS_UNSPECIFIED, + s->txbuf + s->pos, txlen); s->pos += txlen; if (stream_desc_eof(&s->desc)) { @@ -336,7 +343,8 @@ static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf, rxlen = len; } - cpu_physical_memory_write(s->desc.buffer_address, buf + pos, rxlen); + address_space_write(&s->dma->as, s->desc.buffer_address, + MEMTXATTRS_UNSPECIFIED, buf + pos, rxlen); len -= rxlen; pos += rxlen; @@ -525,6 +533,7 @@ static void xilinx_axidma_realize(DeviceState *dev, Error **errp) XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM( &s->rx_control_dev); Error *local_err = NULL; + int i; object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA, (Object **)&ds->dma, @@ -545,17 +554,19 @@ static void xilinx_axidma_realize(DeviceState *dev, Error **errp) goto xilinx_axidma_realize_fail; } - int i; - for (i = 0; i < 2; i++) { struct Stream *st = &s->streams[i]; + st->dma = s; st->nr = i; st->ptimer = ptimer_init(timer_hit, st, PTIMER_POLICY_DEFAULT); ptimer_transaction_begin(st->ptimer); ptimer_set_freq(st->ptimer, s->freqhz); ptimer_transaction_commit(st->ptimer); } + + address_space_init(&s->as, + s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); return; xilinx_axidma_realize_fail: @@ -575,6 +586,11 @@ static void xilinx_axidma_init(Object *obj) &s->rx_control_dev, sizeof(s->rx_control_dev), TYPE_XILINX_AXI_DMA_CONTROL_STREAM, &error_abort, NULL); + object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, + (Object **)&s->dma_mr, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG, + &error_abort); sysbus_init_irq(sbd, &s->streams[0].irq); sysbus_init_irq(sbd, &s->streams[1].irq); From 51b19950ca62abce05b00eef30d9ebbfb8b15f46 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Wed, 6 May 2020 10:25:09 +0200 Subject: [PATCH 05/14] hw/core: stream: Add an end-of-packet flag Some stream clients stream an endless stream of data while other clients stream data in packets. Stream interfaces usually have a way to signal the end of a packet or the last beat of a transfer. This adds an end-of-packet flag to the push interface. Reviewed-by: Alistair Francis Reviewed-by: Francisco Iglesias Signed-off-by: Edgar E. Iglesias Message-Id: <20200506082513.18751-6-edgar.iglesias@gmail.com> --- hw/core/stream.c | 4 ++-- hw/dma/xilinx_axidma.c | 10 ++++++---- hw/net/xilinx_axienet.c | 14 ++++++++++---- hw/ssi/xilinx_spips.c | 2 +- include/hw/stream.h | 5 +++-- 5 files changed, 22 insertions(+), 13 deletions(-) diff --git a/hw/core/stream.c b/hw/core/stream.c index 39b1e595cd..a65ad1208d 100644 --- a/hw/core/stream.c +++ b/hw/core/stream.c @@ -3,11 +3,11 @@ #include "qemu/module.h" size_t -stream_push(StreamSlave *sink, uint8_t *buf, size_t len) +stream_push(StreamSlave *sink, uint8_t *buf, size_t len, bool eop) { StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink); - return k->push(sink, buf, len); + return k->push(sink, buf, len, eop); } bool diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 4540051448..a770e12c96 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -283,7 +283,7 @@ static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev, if (stream_desc_sof(&s->desc)) { s->pos = 0; - stream_push(tx_control_dev, s->desc.app, sizeof(s->desc.app)); + stream_push(tx_control_dev, s->desc.app, sizeof(s->desc.app), true); } txlen = s->desc.control & SDESC_CTRL_LEN_MASK; @@ -298,7 +298,7 @@ static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev, s->pos += txlen; if (stream_desc_eof(&s->desc)) { - stream_push(tx_data_dev, s->txbuf, s->pos); + stream_push(tx_data_dev, s->txbuf, s->pos, true); s->pos = 0; stream_complete(s); } @@ -384,7 +384,7 @@ static void xilinx_axidma_reset(DeviceState *dev) static size_t xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf, - size_t len) + size_t len, bool eop) { XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj); struct Stream *s = &cs->dma->streams[1]; @@ -416,12 +416,14 @@ xilinx_axidma_data_stream_can_push(StreamSlave *obj, } static size_t -xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len) +xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len, + bool eop) { XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj); struct Stream *s = &ds->dma->streams[1]; size_t ret; + assert(eop); ret = stream_process_s2mem(s, buf, len); stream_update_irq(s); return ret; diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index c8dfcda3ee..bd48305577 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -697,14 +697,14 @@ static void axienet_eth_rx_notify(void *opaque) axienet_eth_rx_notify, s)) { size_t ret = stream_push(s->tx_control_dev, (void *)s->rxapp + CONTROL_PAYLOAD_SIZE - - s->rxappsize, s->rxappsize); + - s->rxappsize, s->rxappsize, true); s->rxappsize -= ret; } while (s->rxsize && stream_can_push(s->tx_data_dev, axienet_eth_rx_notify, s)) { size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos, - s->rxsize); + s->rxsize, true); s->rxsize -= ret; s->rxpos += ret; if (!s->rxsize) { @@ -874,12 +874,14 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) } static size_t -xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len) +xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len, + bool eop) { int i; XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj); XilinxAXIEnet *s = cs->enet; + assert(eop); if (len != CONTROL_PAYLOAD_SIZE) { hw_error("AXI Enet requires %d byte control stream payload\n", (int)CONTROL_PAYLOAD_SIZE); @@ -894,11 +896,15 @@ xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len) } static size_t -xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size) +xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, + bool eop) { XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj); XilinxAXIEnet *s = ds->enet; + /* We don't support fragmented packets yet. */ + assert(eop); + /* TX enable ? */ if (!(s->tc & TC_TX)) { return size; diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index c57850a505..4cfce882ab 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -868,7 +868,7 @@ static void xlnx_zynqmp_qspips_notify(void *opaque) memcpy(rq->dma_buf, rxd, num); - ret = stream_push(rq->dma, rq->dma_buf, num); + ret = stream_push(rq->dma, rq->dma_buf, num, false); assert(ret == num); xlnx_zynqmp_qspips_check_flush(rq); } diff --git a/include/hw/stream.h b/include/hw/stream.h index d02f62ca89..ed09e83683 100644 --- a/include/hw/stream.h +++ b/include/hw/stream.h @@ -39,12 +39,13 @@ typedef struct StreamSlaveClass { * @obj: Stream slave to push to * @buf: Data to write * @len: Maximum number of bytes to write + * @eop: End of packet flag */ - size_t (*push)(StreamSlave *obj, unsigned char *buf, size_t len); + size_t (*push)(StreamSlave *obj, unsigned char *buf, size_t len, bool eop); } StreamSlaveClass; size_t -stream_push(StreamSlave *sink, uint8_t *buf, size_t len); +stream_push(StreamSlave *sink, uint8_t *buf, size_t len, bool eop); bool stream_can_push(StreamSlave *sink, StreamCanPushNotifyFn notify, From 2a4f26350c53f9f48d0245254d7af0c55a1d22fe Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Wed, 6 May 2020 10:25:10 +0200 Subject: [PATCH 06/14] hw/net/xilinx_axienet: Handle fragmented packets from DMA Add support for fragmented packets from the DMA. Reviewed-by: Francisco Iglesias Signed-off-by: Edgar E. Iglesias Message-Id: <20200506082513.18751-7-edgar.iglesias@gmail.com> --- hw/net/xilinx_axienet.c | 38 +++++++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index bd48305577..498afe2f54 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -402,6 +402,9 @@ struct XilinxAXIEnet { uint32_t hdr[CONTROL_PAYLOAD_WORDS]; + uint8_t *txmem; + uint32_t txpos; + uint8_t *rxmem; uint32_t rxsize; uint32_t rxpos; @@ -421,6 +424,7 @@ static void axienet_rx_reset(XilinxAXIEnet *s) static void axienet_tx_reset(XilinxAXIEnet *s) { s->tc = TC_JUM | TC_TX | TC_VLAN; + s->txpos = 0; } static inline int axienet_rx_resetting(XilinxAXIEnet *s) @@ -902,17 +906,35 @@ xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj); XilinxAXIEnet *s = ds->enet; - /* We don't support fragmented packets yet. */ - assert(eop); - /* TX enable ? */ if (!(s->tc & TC_TX)) { return size; } + if (s->txpos + size > s->c_txmem) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Packet larger than txmem\n", + TYPE_XILINX_AXI_ENET); + s->txpos = 0; + return size; + } + + if (s->txpos == 0 && eop) { + /* Fast path single fragment. */ + s->txpos = size; + } else { + memcpy(s->txmem + s->txpos, buf, size); + buf = s->txmem; + s->txpos += size; + + if (!eop) { + return size; + } + } + /* Jumbo or vlan sizes ? */ if (!(s->tc & TC_JUM)) { - if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) { + if (s->txpos > 1518 && s->txpos <= 1522 && !(s->tc & TC_VLAN)) { + s->txpos = 0; return size; } } @@ -923,7 +945,7 @@ xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, uint32_t tmp_csum; uint16_t csum; - tmp_csum = net_checksum_add(size - start_off, + tmp_csum = net_checksum_add(s->txpos - start_off, buf + start_off); /* Accumulate the seed. */ tmp_csum += s->hdr[2] & 0xffff; @@ -936,12 +958,13 @@ xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, buf[write_off + 1] = csum & 0xff; } - qemu_send_packet(qemu_get_queue(s->nic), buf, size); + qemu_send_packet(qemu_get_queue(s->nic), buf, s->txpos); - s->stats.tx_bytes += size; + s->stats.tx_bytes += s->txpos; s->regs[R_IS] |= IS_TX_COMPLETE; enet_update_irq(s); + s->txpos = 0; return size; } @@ -989,6 +1012,7 @@ static void xilinx_enet_realize(DeviceState *dev, Error **errp) s->TEMAC.parent = s; s->rxmem = g_malloc(s->c_rxmem); + s->txmem = g_malloc(s->c_txmem); return; xilinx_enet_realize_fail: From 471fe8a2520272253adec1cc099e26f04958e301 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Wed, 6 May 2020 10:25:11 +0200 Subject: [PATCH 07/14] hw/dma/xilinx_axidma: mm2s: Stream descriptor by descriptor Stream descriptor by descriptor from memory instead of buffering entire packets before pushing. This enables non-packet streaming clients to work and also lifts the limitation that our internal DMA buffer needs to be able to hold entire packets. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias Message-Id: <20200506082513.18751-8-edgar.iglesias@gmail.com> --- hw/dma/xilinx_axidma.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index a770e12c96..101d32a965 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -111,7 +111,6 @@ struct Stream { int nr; struct SDesc desc; - int pos; unsigned int complete_cnt; uint32_t regs[R_MAX]; uint8_t app[20]; @@ -267,7 +266,9 @@ static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev, StreamSlave *tx_control_dev) { uint32_t prev_d; - unsigned int txlen; + uint32_t txlen; + uint64_t addr; + bool eop; if (!stream_running(s) || stream_idle(s)) { return; @@ -282,24 +283,26 @@ static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev, } if (stream_desc_sof(&s->desc)) { - s->pos = 0; stream_push(tx_control_dev, s->desc.app, sizeof(s->desc.app), true); } txlen = s->desc.control & SDESC_CTRL_LEN_MASK; - if ((txlen + s->pos) > sizeof s->txbuf) { - hw_error("%s: too small internal txbuf! %d\n", __func__, - txlen + s->pos); + + eop = stream_desc_eof(&s->desc); + addr = s->desc.buffer_address; + while (txlen) { + unsigned int len; + + len = txlen > sizeof s->txbuf ? sizeof s->txbuf : txlen; + address_space_read(&s->dma->as, addr, + MEMTXATTRS_UNSPECIFIED, + s->txbuf, len); + stream_push(tx_data_dev, s->txbuf, len, eop && len == txlen); + txlen -= len; + addr += len; } - address_space_read(&s->dma->as, s->desc.buffer_address, - MEMTXATTRS_UNSPECIFIED, - s->txbuf + s->pos, txlen); - s->pos += txlen; - - if (stream_desc_eof(&s->desc)) { - stream_push(tx_data_dev, s->txbuf, s->pos, true); - s->pos = 0; + if (eop) { stream_complete(s); } From 734e3befc20b699c69a6e20feade8073b1c19838 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Wed, 6 May 2020 10:25:12 +0200 Subject: [PATCH 08/14] hw/dma/xilinx_axidma: s2mm: Support stream fragments Add support for stream fragments. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias Message-Id: <20200506082513.18751-9-edgar.iglesias@gmail.com> --- hw/dma/xilinx_axidma.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 101d32a965..87be9cade7 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -110,6 +110,7 @@ struct Stream { int nr; + bool sof; struct SDesc desc; unsigned int complete_cnt; uint32_t regs[R_MAX]; @@ -174,6 +175,7 @@ static void stream_reset(struct Stream *s) { s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */ s->regs[R_DMACR] = 1 << 16; /* Starts with one in compl threshold. */ + s->sof = true; } /* Map an offset addr into a channel index. */ @@ -321,12 +323,11 @@ static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev, } static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf, - size_t len) + size_t len, bool eop) { uint32_t prev_d; unsigned int rxlen; size_t pos = 0; - int sof = 1; if (!stream_running(s) || stream_idle(s)) { return 0; @@ -352,16 +353,16 @@ static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf, pos += rxlen; /* Update the descriptor. */ - if (!len) { + if (eop) { stream_complete(s); memcpy(s->desc.app, s->app, sizeof(s->desc.app)); s->desc.status |= SDESC_STATUS_EOF; } - s->desc.status |= sof << SDESC_STATUS_SOF_BIT; + s->desc.status |= s->sof << SDESC_STATUS_SOF_BIT; s->desc.status |= SDESC_STATUS_COMPLETE; stream_desc_store(s, s->regs[R_CURDESC]); - sof = 0; + s->sof = eop; /* Advance. */ prev_d = s->regs[R_CURDESC]; @@ -426,8 +427,7 @@ xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len, struct Stream *s = &ds->dma->streams[1]; size_t ret; - assert(eop); - ret = stream_process_s2mem(s, buf, len); + ret = stream_process_s2mem(s, buf, len, eop); stream_update_irq(s); return ret; } From 6d0af39f81cd22c7d26fd00e262d722e0003014f Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Wed, 6 May 2020 10:25:13 +0200 Subject: [PATCH 09/14] MAINTAINERS: Add myself as streams maintainer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since we're missing a maintainer, add myself. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200506082513.18751-10-edgar.iglesias@gmail.com> --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 005ee98a59..d11f3cb976 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2315,6 +2315,12 @@ F: net/slirp.c F: include/net/slirp.h T: git https://people.debian.org/~sthibault/qemu.git slirp +Streams +M: Edgar E. Iglesias +S: Maintained +F: hw/core/stream.c +F: include/hw/stream.h + Stubs M: Paolo Bonzini S: Maintained From 7cdae31d3a654d6487727809b27dd8e88874fd50 Mon Sep 17 00:00:00 2001 From: Tong Ho Date: Tue, 12 May 2020 16:36:49 +0200 Subject: [PATCH 10/14] target/microblaze: Add MFS Rd,EDR translation This is to fix cpu-abort with 'qemu: fatal: unknown mfs reg d' (in the default case) when microblaze guest issues 'MFS Rd,EDR' instruction. Since embeddedsw release 2019.2, XPlm_ExceptionHandler() issues the instruction on exception, and microblaze model aborts when PLM firmware guest encounters an exception. Signed-off-by: Tong Ho Reviewed-by: Edgar E. Iglesias Reviewed-by: Luc Michel Message-Id: <20200512143649.21655-2-edgar.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 20b7427811..92b3630804 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -581,6 +581,7 @@ static void dec_msr(DisasContext *dc) case SR_ESR: case SR_FSR: case SR_BTR: + case SR_EDR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); break; case 0x800: From 2016a6a765ad5283609183a5aa14d14285aaca6e Mon Sep 17 00:00:00 2001 From: Joe Komlodi Date: Mon, 11 May 2020 10:49:06 -0700 Subject: [PATCH 11/14] target/microblaze: Fix FPU2 instruction check The check to see if we can use FPU2 instructions would return 0 if cfg.use_fpu == 2, rather than returning the PVR2_USE_FPU2_MASK. This would cause all FPU2 instructions (fsqrt, flt, fint) to not be used. Signed-off-by: Joe Komlodi Reviewed-by: Edgar E. Iglesias Message-Id: <1589219346-106769-2-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 92b3630804..8079724f32 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1392,7 +1392,7 @@ static int dec_check_fpuv2(DisasContext *dc) tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } - return (dc->cpu->cfg.use_fpu == 2) ? 0 : PVR2_USE_FPU2_MASK; + return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; } static void dec_fpu(DisasContext *dc) From a44e82db0c0bada34af613029cf976f8bb7859d9 Mon Sep 17 00:00:00 2001 From: Joe Komlodi Date: Wed, 13 May 2020 11:08:46 -0700 Subject: [PATCH 12/14] target/microblaze: gdb: Extend the number of registers presented to GDB Increase the number of Microblaze registers QEMU will report when talking to GDB. Signed-off-by: Joe Komlodi Reviewed-by: Edgar E. Iglesias Message-Id: <1589393329-223076-2-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 2 +- target/microblaze/gdbstub.c | 52 ++++++++++++++++++++++++++++++++++--- 2 files changed, 50 insertions(+), 4 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index aa9983069a..51e5c85b10 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -329,7 +329,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) #endif dc->vmsd = &vmstate_mb_cpu; device_class_set_props(dc, mb_properties); - cc->gdb_num_core_regs = 32 + 5; + cc->gdb_num_core_regs = 32 + 27; cc->disas_set_info = mb_disas_set_info; cc->tcg_initialize = mb_tcg_init; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index f41ebf1f33..54cc7857d1 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -26,12 +26,37 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; + /* + * GDB expects registers to be reported in this order: + * R0-R31 + * PC-BTR + * PVR0-PVR11 + * EDR-TLBHI + * SLR-SHR + */ if (n < 32) { return gdb_get_reg32(mem_buf, env->regs[n]); } else { - return gdb_get_reg32(mem_buf, env->sregs[n - 32]); + n -= 32; + switch (n) { + case 0 ... 5: + return gdb_get_reg32(mem_buf, env->sregs[n]); + /* PVR12 is intentionally skipped */ + case 6 ... 17: + n -= 6; + return gdb_get_reg32(mem_buf, env->pvr.regs[n]); + case 18 ... 24: + /* Add an offset of 6 to resume where we left off with SRegs */ + n = n - 18 + 6; + return gdb_get_reg32(mem_buf, env->sregs[n]); + case 25: + return gdb_get_reg32(mem_buf, env->slr); + case 26: + return gdb_get_reg32(mem_buf, env->shr); + default: + return 0; + } } - return 0; } int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) @@ -50,7 +75,28 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) if (n < 32) { env->regs[n] = tmp; } else { - env->sregs[n - 32] = tmp; + n -= 32; + switch (n) { + case 0 ... 5: + env->sregs[n] = tmp; + break; + /* PVR12 is intentionally skipped */ + case 6 ... 17: + n -= 6; + env->pvr.regs[n] = tmp; + break; + case 18 ... 24: + /* Add an offset of 6 to resume where we left off with SRegs */ + n = n - 18 + 6; + env->sregs[n] = tmp; + break; + case 25: + env->slr = tmp; + break; + case 26: + env->shr = tmp; + break; + } } return 4; } From 201dd7d37b654621c5727e49c666cbfc56e61d58 Mon Sep 17 00:00:00 2001 From: Joe Komlodi Date: Wed, 13 May 2020 11:08:47 -0700 Subject: [PATCH 13/14] target/microblaze: gdb: Fix incorrect SReg reporting SRegs used to be reported to GDB by iterating over the SRegs array, however we do not store them in an order that allows them to be reported to GDB in that way. To fix this, a simple map is used to map the register GDB wants to its location in the SRegs array. Signed-off-by: Joe Komlodi Reviewed-by: Edgar E. Iglesias Message-Id: <1589393329-223076-3-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias --- target/microblaze/gdbstub.c | 59 ++++++++++++++++++++++++++++++------- 1 file changed, 49 insertions(+), 10 deletions(-) diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 54cc7857d1..73e8973597 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -25,6 +25,21 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; + /* + * GDB expects SREGs in the following order: + * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. + * They aren't stored in this order, so make a map. + * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't + * map them to anything and return a value of 0 instead. + */ + static const uint8_t sreg_map[6] = { + SR_PC, + SR_MSR, + SR_EAR, + SR_ESR, + SR_FSR, + SR_BTR + }; /* * GDB expects registers to be reported in this order: @@ -40,15 +55,16 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) n -= 32; switch (n) { case 0 ... 5: - return gdb_get_reg32(mem_buf, env->sregs[n]); + return gdb_get_reg32(mem_buf, env->sregs[sreg_map[n]]); /* PVR12 is intentionally skipped */ case 6 ... 17: n -= 6; return gdb_get_reg32(mem_buf, env->pvr.regs[n]); - case 18 ... 24: - /* Add an offset of 6 to resume where we left off with SRegs */ - n = n - 18 + 6; - return gdb_get_reg32(mem_buf, env->sregs[n]); + case 18: + return gdb_get_reg32(mem_buf, env->sregs[SR_EDR]); + /* Other SRegs aren't modeled, so report a value of 0 */ + case 19 ... 24: + return gdb_get_reg32(mem_buf, 0); case 25: return gdb_get_reg32(mem_buf, env->slr); case 26: @@ -66,29 +82,52 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) CPUMBState *env = &cpu->env; uint32_t tmp; + /* + * GDB expects SREGs in the following order: + * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. + * They aren't stored in this order, so make a map. + * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't + * map them to anything. + */ + static const uint8_t sreg_map[6] = { + SR_PC, + SR_MSR, + SR_EAR, + SR_ESR, + SR_FSR, + SR_BTR + }; + if (n > cc->gdb_num_core_regs) { return 0; } tmp = ldl_p(mem_buf); + /* + * GDB expects registers to be reported in this order: + * R0-R31 + * PC-BTR + * PVR0-PVR11 + * EDR-TLBHI + * SLR-SHR + */ if (n < 32) { env->regs[n] = tmp; } else { n -= 32; switch (n) { case 0 ... 5: - env->sregs[n] = tmp; + env->sregs[sreg_map[n]] = tmp; break; /* PVR12 is intentionally skipped */ case 6 ... 17: n -= 6; env->pvr.regs[n] = tmp; break; - case 18 ... 24: - /* Add an offset of 6 to resume where we left off with SRegs */ - n = n - 18 + 6; - env->sregs[n] = tmp; + /* Only EDR is modeled in these indeces, so ignore the rest */ + case 18: + env->sregs[SR_EDR] = tmp; break; case 25: env->slr = tmp; From 2ead1b18ca1bbc41c09a82d980e1e5f53afa08eb Mon Sep 17 00:00:00 2001 From: Joe Komlodi Date: Wed, 13 May 2020 11:08:48 -0700 Subject: [PATCH 14/14] target/microblaze: monitor: Increase the number of registers reported Increase the number of registers reported to match GDB. Registers that aren't modeled are reported as 0. Signed-off-by: Joe Komlodi Reviewed-by: Edgar E. Iglesias Message-Id: <1589393329-223076-4-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 8079724f32..f6ff2591c3 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1789,9 +1789,11 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%" PRIx64 " %s\n", env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC])); qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " - "debug=%x imm=%x iflags=%x fsr=%" PRIx64 "\n", + "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " + "rbtr=%" PRIx64 "\n", env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], - env->debug, env->imm, env->iflags, env->sregs[SR_FSR]); + env->debug, env->imm, env->iflags, env->sregs[SR_FSR], + env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " "eip=%d ie=%d\n", env->btaken, env->btarget, @@ -1799,7 +1801,17 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", (bool)(env->sregs[SR_MSR] & MSR_EIP), (bool)(env->sregs[SR_MSR] & MSR_IE)); + for (i = 0; i < 12; i++) { + qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]); + if ((i + 1) % 4 == 0) { + qemu_fprintf(f, "\n"); + } + } + /* Registers that aren't modeled are reported as 0 */ + qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " + "rtlblo=0 rtlbhi=0\n", env->sregs[SR_EDR]); + qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); for (i = 0; i < 32; i++) { qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); if ((i + 1) % 4 == 0)