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target/mips: Clean up handling of CP0 register 31

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Clean up handling of CP0 register 31.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-31-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic 2019-08-28 18:26:54 +02:00
parent 4bcf121ebb
commit 14d92efd72
2 changed files with 29 additions and 29 deletions
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2
target/mips/cpu.h
View File

@ -613,7 +613,6 @@ struct CPUMIPSState {
* CP0 Register 4
*/
target_ulong CP0_Context;
target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
int32_t CP0_MemoryMapID;
/*
* CP0 Register 5
@ -1024,6 +1023,7 @@ struct CPUMIPSState {
* CP0 Register 31
*/
int32_t CP0_DESAVE;
target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
/* We waste some space so we can handle shadow registers like TCs. */
TCState tcs[MIPS_SHADOW_SET_MAX];

56
target/mips/translate.c
View File

@ -7532,17 +7532,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
case 0:
case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case CP0_REG31__KSCRATCH1:
case CP0_REG31__KSCRATCH2:
case CP0_REG31__KSCRATCH3:
case CP0_REG31__KSCRATCH4:
case CP0_REG31__KSCRATCH5:
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@ -8282,17 +8282,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
case 0:
case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case CP0_REG31__KSCRATCH1:
case CP0_REG31__KSCRATCH2:
case CP0_REG31__KSCRATCH3:
case CP0_REG31__KSCRATCH4:
case CP0_REG31__KSCRATCH5:
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@ -9009,17 +9009,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
case 0:
case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case CP0_REG31__KSCRATCH1:
case CP0_REG31__KSCRATCH2:
case CP0_REG31__KSCRATCH3:
case CP0_REG31__KSCRATCH4:
case CP0_REG31__KSCRATCH5:
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@ -9746,17 +9746,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
case 0:
case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case CP0_REG31__KSCRATCH1:
case CP0_REG31__KSCRATCH2:
case CP0_REG31__KSCRATCH3:
case CP0_REG31__KSCRATCH4:
case CP0_REG31__KSCRATCH5:
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));