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https://github.com/xemu-project/xemu.git
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More TCG updates for CRIS
* Convert parts of the jump logic to TCG. * Stores no longer have to go via T0/T1. * Use the byte and halfword ldx_code variants when appropriate for insn fetching. * Do not disassemble beyond the translation block. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4350 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
ef29a70d18
commit
17ac975463
@ -235,7 +235,7 @@ static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
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l1 = gen_new_label();
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/* Speculative shift. */
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tcg_gen_shl_tl(d, a, b);
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tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
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tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
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/* Clear dst if shift operands were to large. */
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tcg_gen_movi_tl(d, 0);
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gen_set_label(l1);
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@ -248,7 +248,7 @@ static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
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l1 = gen_new_label();
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/* Speculative shift. */
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tcg_gen_shr_tl(d, a, b);
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tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
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tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
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/* Clear dst if shift operands were to large. */
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tcg_gen_movi_tl(d, 0);
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gen_set_label(l1);
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@ -261,7 +261,7 @@ static void t_gen_asr(TCGv d, TCGv a, TCGv b)
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l1 = gen_new_label();
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/* Speculative shift. */
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tcg_gen_sar_tl(d, a, b);
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tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
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tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
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/* Clear dst if shift operands were to large. */
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tcg_gen_sar_tl(d, a, tcg_const_tl(30));
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gen_set_label(l1);
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@ -528,6 +528,24 @@ static inline void t_gen_swapr(TCGv d, TCGv s)
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tcg_gen_discard_tl(org_s);
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}
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static void t_gen_cc_jmp(target_ulong pc_true, target_ulong pc_false)
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{
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TCGv btaken;
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int l1;
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l1 = gen_new_label();
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btaken = tcg_temp_new(TCG_TYPE_TL);
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/* Conditional jmp. */
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t_gen_mov_TN_env(btaken, btaken);
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tcg_gen_movi_tl(env_pc, pc_false);
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tcg_gen_brcond_tl(TCG_COND_EQ, btaken, tcg_const_tl(0), l1);
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tcg_gen_movi_tl(env_pc, pc_true);
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gen_set_label(l1);
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tcg_gen_discard_tl(btaken);
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}
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static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
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{
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TranslationBlock *tb;
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@ -908,7 +926,7 @@ static void gen_tst_cc (DisasContext *dc, int cond)
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break;
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case CC_A:
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cris_evaluate_flags(dc);
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gen_op_movl_T0_im (1);
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tcg_gen_movi_tl(cpu_T[0], 1);
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break;
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default:
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BUG();
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@ -957,8 +975,6 @@ void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
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{
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int mem_index = cpu_mmu_index(dc->env);
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/* FIXME: qemu_ld does not act as a barrier? */
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tcg_gen_helper_0_0(helper_dummy);
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cris_evaluate_flags(dc);
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if (size == 1) {
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if (sign)
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@ -977,21 +993,20 @@ void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
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}
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}
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void gen_store_T0_T1 (DisasContext *dc, unsigned int size)
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void gen_store (DisasContext *dc, TCGv addr, TCGv val,
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unsigned int size)
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{
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int mem_index = cpu_mmu_index(dc->env);
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/* FIXME: qemu_st does not act as a barrier? */
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tcg_gen_helper_0_0(helper_dummy);
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cris_evaluate_flags(dc);
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/* Remember, operands are flipped. CRIS has reversed order. */
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if (size == 1)
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tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], mem_index);
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tcg_gen_qemu_st8(val, addr, mem_index);
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else if (size == 2)
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tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], mem_index);
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tcg_gen_qemu_st16(val, addr, mem_index);
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else
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tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], mem_index);
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tcg_gen_qemu_st32(val, addr, mem_index);
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}
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static inline void t_gen_sext(TCGv d, TCGv s, int size)
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@ -1096,22 +1111,28 @@ static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
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if (memsize == 1)
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insn_len++;
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imm = ldl_code(dc->pc + 2);
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if (memsize != 4) {
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if (s_ext) {
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imm = sign_extend(imm, (memsize * 8) - 1);
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if (memsize == 1)
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imm = ldsb_code(dc->pc + 2);
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else
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imm = ldsw_code(dc->pc + 2);
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} else {
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if (memsize == 1)
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imm &= 0xff;
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imm = ldub_code(dc->pc + 2);
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else
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imm &= 0xffff;
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imm = lduw_code(dc->pc + 2);
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}
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}
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} else
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imm = ldl_code(dc->pc + 2);
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DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
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imm, rd, s_ext, memsize));
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tcg_gen_movi_tl(cpu_T[1], imm);
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dc->postinc = 0;
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} else {
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/* FIXME: qemu_ld does not act as a barrier? */
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tcg_gen_helper_0_0(helper_dummy);
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gen_load(dc, cpu_T[1], cpu_R[rs], memsize, 0);
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if (s_ext)
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t_gen_sext(cpu_T[1], cpu_T[1], memsize);
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@ -1250,6 +1271,8 @@ static unsigned int dec_btstq(DisasContext *dc)
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{
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dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
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DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
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cris_evaluate_flags(dc);
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cris_cc_mask(dc, CC_MASK_NZ);
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t_gen_mov_TN_reg(cpu_T[0], dc->op2);
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t_gen_mov_TN_im(cpu_T[1], dc->op1);
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@ -1601,6 +1624,7 @@ static unsigned int dec_btst_r(DisasContext *dc)
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{
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DIS(fprintf (logfile, "btst $r%u, $r%u\n",
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dc->op1, dc->op2));
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cris_evaluate_flags(dc);
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cris_cc_mask(dc, CC_MASK_NZ);
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dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
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crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
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@ -2162,36 +2186,47 @@ static unsigned int dec_move_pm(DisasContext *dc)
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dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
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/* prepare store. Address in T0, value in T1. */
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if (dc->op2 == PR_CCS)
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cris_evaluate_flags(dc);
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t_gen_mov_TN_preg(cpu_T[1], dc->op2);
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t_gen_mov_TN_reg(cpu_T[0], dc->op1);
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gen_store_T0_T1(dc, memsize);
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/* FIXME: qemu_st does not act as a barrier? */
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tcg_gen_helper_0_0(helper_dummy);
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gen_store(dc, cpu_R[dc->op1], cpu_T[1], memsize);
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cris_cc_mask(dc, 0);
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if (dc->postinc)
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{
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tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize);
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t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
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}
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tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
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return 2;
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}
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static unsigned int dec_movem_mr(DisasContext *dc)
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{
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TCGv tmp[16];
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int i;
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DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
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dc->postinc ? "+]" : "]", dc->op2));
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/* FIXME: qemu_ld does not act as a barrier? */
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tcg_gen_helper_0_0(helper_dummy);
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/* fetch the address into T0 and T1. */
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t_gen_mov_TN_reg(cpu_T[1], dc->op1);
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for (i = 0; i <= dc->op2; i++) {
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tmp[i] = tcg_temp_new(TCG_TYPE_TL);
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/* Perform the load onto regnum i. Always dword wide. */
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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gen_load(dc, cpu_R[i], cpu_T[1], 4, 0);
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tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 4);
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tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
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gen_load(dc, tmp[i], cpu_T[0], 4, 0);
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}
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for (i = 0; i <= dc->op2; i++) {
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tcg_gen_mov_tl(cpu_R[i], tmp[i]);
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tcg_gen_discard_tl(tmp[i]);
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}
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/* writeback the updated pointer value. */
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if (dc->postinc)
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t_gen_mov_reg_TN(dc->op1, cpu_T[1]);
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tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
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/* gen_load might want to evaluate the previous insns flags. */
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cris_cc_mask(dc, 0);
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@ -2205,23 +2240,17 @@ static unsigned int dec_movem_rm(DisasContext *dc)
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DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
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dc->postinc ? "+]" : "]"));
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/* FIXME: qemu_st does not act as a barrier? */
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tcg_gen_helper_0_0(helper_dummy);
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for (i = 0; i <= dc->op2; i++) {
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/* Fetch register i into T1. */
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t_gen_mov_TN_reg(cpu_T[1], i);
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/* Fetch the address into T0. */
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t_gen_mov_TN_reg(cpu_T[0], dc->op1);
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/* Displace it. */
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tcg_gen_addi_tl(cpu_T[0], cpu_T[0], i * 4);
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/* Displace addr. */
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tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
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/* Perform the store. */
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gen_store_T0_T1(dc, 4);
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}
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if (dc->postinc) {
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/* T0 should point to the last written addr, advance one more
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step. */
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tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 4);
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/* writeback the updated pointer value. */
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t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
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gen_store(dc, cpu_T[0], cpu_R[i], 4);
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}
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if (dc->postinc)
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tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
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cris_cc_mask(dc, 0);
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return 2;
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}
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@ -2236,14 +2265,12 @@ static unsigned int dec_move_rm(DisasContext *dc)
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memsize, dc->op2, dc->op1));
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/* prepare store. */
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t_gen_mov_TN_reg(cpu_T[0], dc->op1);
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t_gen_mov_TN_reg(cpu_T[1], dc->op2);
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gen_store_T0_T1(dc, memsize);
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/* FIXME: qemu_st does not act as a barrier? */
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tcg_gen_helper_0_0(helper_dummy);
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gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
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if (dc->postinc)
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{
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tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize);
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t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
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}
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tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
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cris_cc_mask(dc, 0);
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return 2;
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}
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@ -2280,11 +2307,13 @@ static unsigned int dec_lapc_im(DisasContext *dc)
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static unsigned int dec_jump_p(DisasContext *dc)
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{
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DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
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cris_cc_mask(dc, 0);
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if (dc->op2 == PR_CCS)
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cris_evaluate_flags(dc);
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t_gen_mov_TN_preg(cpu_T[0], dc->op2);
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/* rete will often have low bit set to indicate delayslot. */
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tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
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cris_cc_mask(dc, 0);
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cris_prepare_dyn_jmp(dc);
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return 2;
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}
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@ -2298,7 +2327,8 @@ static unsigned int dec_jas_r(DisasContext *dc)
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tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
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if (dc->op2 > 15)
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abort();
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tcg_gen_movi_tl(cpu_PR[dc->op2], dc->pc + 4);
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tcg_gen_movi_tl(cpu_T[0], dc->pc + 4);
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tcg_gen_mov_tl(cpu_PR[dc->op2], cpu_T[0]);
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cris_prepare_dyn_jmp(dc);
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return 2;
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@ -2312,7 +2342,7 @@ static unsigned int dec_jas_im(DisasContext *dc)
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DIS(fprintf (logfile, "jas 0x%x\n", imm));
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cris_cc_mask(dc, 0);
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/* Stor the return address in Pd. */
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/* Store the return address in Pd. */
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tcg_gen_movi_tl(env_btarget, imm);
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t_gen_mov_preg_TN(dc->op2, tcg_const_tl(dc->pc + 8));
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cris_prepare_dyn_jmp(dc);
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@ -2327,7 +2357,7 @@ static unsigned int dec_jasc_im(DisasContext *dc)
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DIS(fprintf (logfile, "jasc 0x%x\n", imm));
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cris_cc_mask(dc, 0);
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/* Stor the return address in Pd. */
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/* Store the return address in Pd. */
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tcg_gen_movi_tl(cpu_T[0], imm);
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t_gen_mov_env_TN(btarget, cpu_T[0]);
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tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
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@ -2340,7 +2370,7 @@ static unsigned int dec_jasc_r(DisasContext *dc)
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{
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DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
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cris_cc_mask(dc, 0);
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/* Stor the return address in Pd. */
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/* Store the return address in Pd. */
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t_gen_mov_TN_reg(cpu_T[0], dc->op1);
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t_gen_mov_env_TN(btarget, cpu_T[0]);
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tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
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@ -2354,8 +2384,7 @@ static unsigned int dec_bcc_im(DisasContext *dc)
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int32_t offset;
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uint32_t cond = dc->op2;
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offset = ldl_code(dc->pc + 2);
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offset = sign_extend(offset, 15);
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offset = ldsw_code(dc->pc + 2);
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DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
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cc_name(cond), offset,
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@ -2579,12 +2608,10 @@ static inline unsigned int
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cris_decoder(DisasContext *dc)
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{
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unsigned int insn_len = 2;
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uint32_t tmp;
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int i;
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/* Load a halfword onto the instruction register. */
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tmp = ldl_code(dc->pc);
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dc->ir = tmp & 0xffff;
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dc->ir = lduw_code(dc->pc);
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/* Now decode it. */
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dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
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@ -2720,12 +2747,11 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
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if (dc->delayed_branch == 0)
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{
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if (dc->bcc == CC_A) {
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gen_op_jmp1 ();
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tcg_gen_mov_tl(env_pc, env_btarget);
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dc->is_jmp = DISAS_JUMP;
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}
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else {
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/* Conditional jmp. */
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gen_op_cc_jmp (dc->delayed_pc, dc->pc);
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t_gen_cc_jmp(dc->delayed_pc, dc->pc);
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dc->is_jmp = DISAS_JUMP;
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}
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}
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@ -2785,7 +2811,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "--------------\n");
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fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
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target_disas(logfile, pc_start, dc->pc + 4 - pc_start, 0);
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target_disas(logfile, pc_start, dc->pc - pc_start, 0);
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fprintf(logfile, "\nisize=%d osize=%d\n",
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dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
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}
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@ -2942,5 +2968,5 @@ void cpu_reset (CPUCRISState *env)
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void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
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unsigned long searched_pc, int pc_pos, void *puc)
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{
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env->pc = gen_opc_pc[pc_pos];
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env->pc = gen_opc_pc[pc_pos];
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}
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