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hw/riscv: virt: Allow creating multiple NUMA sockets
We extend RISC-V virt machine to allow creating a multi-socket machine. Each RISC-V virt machine socket is a NUMA node having a set of HARTs, a memory instance, a CLINT instance, and a PLIC instance. Other devices are shared between all sockets. We also update the generated device tree accordingly. By default, NUMA multi-socket support is disabled for RISC-V virt machine. To enable it, users can use "-numa" command-line options of QEMU. Example1: For two NUMA nodes with 2 CPUs each, append following to command-line options: "-smp 4 -numa node -numa node" Example2: For two NUMA nodes with 1 and 3 CPUs, append following to command-line options: "-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \ -numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \ -numa cpu,node-id=1,core-id=3" The maximum number of sockets in a RISC-V virt machine is 8 but this limit can be changed in future. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Message-Id: <20200616032229.766089-6-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel
Alistair Francis
parent
a7172791e3
commit
18df0b4695
522
hw/riscv/virt.c
522
hw/riscv/virt.c
@ -35,6 +35,7 @@
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#include "hw/riscv/sifive_test.h"
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#include "hw/riscv/virt.h"
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#include "hw/riscv/boot.h"
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#include "hw/riscv/numa.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/device_tree.h"
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@ -58,7 +59,7 @@ static const struct MemmapEntry {
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[VIRT_RTC] = { 0x101000, 0x1000 },
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[VIRT_CLINT] = { 0x2000000, 0x10000 },
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[VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
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[VIRT_PLIC] = { 0xc000000, 0x4000000 },
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[VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
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[VIRT_UART0] = { 0x10000000, 0x100 },
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[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
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[VIRT_FLASH] = { 0x20000000, 0x4000000 },
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@ -179,10 +180,17 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
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uint64_t mem_size, const char *cmdline)
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{
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void *fdt;
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int cpu, i;
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uint32_t *cells;
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char *nodename;
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uint32_t plic_phandle, test_phandle, phandle = 1;
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int i, cpu, socket;
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MachineState *mc = MACHINE(s);
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uint64_t addr, size;
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uint32_t *clint_cells, *plic_cells;
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unsigned long clint_addr, plic_addr;
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uint32_t plic_phandle[MAX_NODES];
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uint32_t cpu_phandle, intc_phandle, test_phandle;
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uint32_t phandle = 1, plic_mmio_phandle = 1;
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uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1;
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char *mem_name, *cpu_name, *core_name, *intc_name;
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char *name, *clint_name, *plic_name, *clust_name;
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hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
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hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
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@ -203,231 +211,238 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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nodename = g_strdup_printf("/memory@%lx",
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(long)memmap[VIRT_DRAM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
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mem_size >> 32, mem_size);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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SIFIVE_CLINT_TIMEBASE_FREQ);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
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int cpu_phandle = phandle++;
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int intc_phandle;
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nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *isa = riscv_isa_string(&s->soc.harts[cpu]);
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qemu_fdt_add_subnode(fdt, nodename);
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#if defined(TARGET_RISCV32)
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
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#else
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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#endif
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
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qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
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intc_phandle = phandle++;
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qemu_fdt_add_subnode(fdt, intc);
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qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
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qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
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g_free(isa);
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g_free(intc);
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g_free(nodename);
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}
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/* Add cpu-topology node */
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qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
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qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0");
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for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
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char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
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cpu);
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char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename);
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qemu_fdt_add_subnode(fdt, core_nodename);
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qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle);
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g_free(core_nodename);
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g_free(cpu_nodename);
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for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
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clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
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qemu_fdt_add_subnode(fdt, clust_name);
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plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
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clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
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for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
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cpu_phandle = phandle++;
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cpu_name = g_strdup_printf("/cpus/cpu@%d",
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s->soc[socket].hartid_base + cpu);
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qemu_fdt_add_subnode(fdt, cpu_name);
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#if defined(TARGET_RISCV32)
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qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
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#else
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qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
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#endif
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name = riscv_isa_string(&s->soc[socket].harts[cpu]);
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qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
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g_free(name);
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qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
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qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
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s->soc[socket].hartid_base + cpu);
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qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
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riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
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qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
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intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
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qemu_fdt_add_subnode(fdt, intc_name);
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intc_phandle = phandle++;
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qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
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qemu_fdt_setprop_string(fdt, intc_name, "compatible",
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"riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
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clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
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plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
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core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
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qemu_fdt_add_subnode(fdt, core_name);
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qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
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g_free(core_name);
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g_free(intc_name);
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g_free(cpu_name);
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}
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addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
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size = riscv_socket_mem_size(mc, socket);
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mem_name = g_strdup_printf("/memory@%lx", (long)addr);
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qemu_fdt_add_subnode(fdt, mem_name);
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qemu_fdt_setprop_cells(fdt, mem_name, "reg",
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addr >> 32, addr, size >> 32, size);
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qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
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riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
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g_free(mem_name);
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clint_addr = memmap[VIRT_CLINT].base +
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(memmap[VIRT_CLINT].size * socket);
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clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
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qemu_fdt_add_subnode(fdt, clint_name);
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qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, clint_name, "reg",
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0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
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qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
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clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
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riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
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g_free(clint_name);
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plic_phandle[socket] = phandle++;
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plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
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plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
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qemu_fdt_add_subnode(fdt, plic_name);
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qemu_fdt_setprop_cell(fdt, plic_name,
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"#address-cells", FDT_PLIC_ADDR_CELLS);
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qemu_fdt_setprop_cell(fdt, plic_name,
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"#interrupt-cells", FDT_PLIC_INT_CELLS);
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qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
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qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
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plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
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qemu_fdt_setprop_cells(fdt, plic_name, "reg",
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0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
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qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
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riscv_socket_fdt_write_id(mc, fdt, plic_name, socket);
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qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]);
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g_free(plic_name);
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g_free(clint_cells);
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g_free(plic_cells);
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g_free(clust_name);
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}
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cells = g_new0(uint32_t, s->soc.num_harts * 4);
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for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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g_free(nodename);
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for (socket = 0; socket < riscv_socket_count(mc); socket++) {
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if (socket == 0) {
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plic_mmio_phandle = plic_phandle[socket];
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plic_virtio_phandle = plic_phandle[socket];
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plic_pcie_phandle = plic_phandle[socket];
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}
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if (socket == 1) {
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plic_virtio_phandle = plic_phandle[socket];
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plic_pcie_phandle = plic_phandle[socket];
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}
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if (socket == 2) {
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plic_pcie_phandle = plic_phandle[socket];
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}
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}
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nodename = g_strdup_printf("/soc/clint@%lx",
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(long)memmap[VIRT_CLINT].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[VIRT_CLINT].base,
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0x0, memmap[VIRT_CLINT].size);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.num_harts * sizeof(uint32_t) * 4);
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g_free(cells);
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g_free(nodename);
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plic_phandle = phandle++;
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cells = g_new0(uint32_t, s->soc.num_harts * 4);
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for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
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(long)memmap[VIRT_PLIC].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
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FDT_PLIC_ADDR_CELLS);
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qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
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FDT_PLIC_INT_CELLS);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
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qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.num_harts * sizeof(uint32_t) * 4);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[VIRT_PLIC].base,
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0x0, memmap[VIRT_PLIC].size);
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qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
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plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
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g_free(cells);
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g_free(nodename);
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riscv_socket_fdt_write_distance_matrix(mc, fdt);
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for (i = 0; i < VIRTIO_COUNT; i++) {
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nodename = g_strdup_printf("/virtio_mmio@%lx",
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name = g_strdup_printf("/soc/virtio_mmio@%lx",
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(long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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qemu_fdt_add_subnode(fdt, name);
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qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio");
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qemu_fdt_setprop_cells(fdt, name, "reg",
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0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
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0x0, memmap[VIRT_VIRTIO].size);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
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g_free(nodename);
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qemu_fdt_setprop_cell(fdt, name, "interrupt-parent",
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plic_virtio_phandle);
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qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i);
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g_free(name);
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}
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nodename = g_strdup_printf("/soc/pci@%lx",
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name = g_strdup_printf("/soc/pci@%lx",
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(long) memmap[VIRT_PCIE_ECAM].base);
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qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
|
||||
FDT_PCI_ADDR_CELLS);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
|
||||
FDT_PCI_INT_CELLS);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible",
|
||||
"pci-host-ecam-generic");
|
||||
qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
|
||||
memmap[VIRT_PCIE_ECAM].size /
|
||||
PCIE_MMCFG_SIZE_MIN - 1);
|
||||
qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
|
||||
0, memmap[VIRT_PCIE_ECAM].size);
|
||||
qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
|
||||
qemu_fdt_add_subnode(fdt, name);
|
||||
qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS);
|
||||
qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS);
|
||||
qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2);
|
||||
qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic");
|
||||
qemu_fdt_setprop_string(fdt, name, "device_type", "pci");
|
||||
qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0);
|
||||
qemu_fdt_setprop_cells(fdt, name, "bus-range", 0,
|
||||
memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
|
||||
qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0);
|
||||
qemu_fdt_setprop_cells(fdt, name, "reg", 0,
|
||||
memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
|
||||
qemu_fdt_setprop_sized_cells(fdt, name, "ranges",
|
||||
1, FDT_PCI_RANGE_IOPORT, 2, 0,
|
||||
2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
|
||||
1, FDT_PCI_RANGE_MMIO,
|
||||
2, memmap[VIRT_PCIE_MMIO].base,
|
||||
2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
|
||||
create_pcie_irq_map(fdt, nodename, plic_phandle);
|
||||
g_free(nodename);
|
||||
create_pcie_irq_map(fdt, name, plic_pcie_phandle);
|
||||
g_free(name);
|
||||
|
||||
test_phandle = phandle++;
|
||||
nodename = g_strdup_printf("/test@%lx",
|
||||
name = g_strdup_printf("/soc/test@%lx",
|
||||
(long)memmap[VIRT_TEST].base);
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_add_subnode(fdt, name);
|
||||
{
|
||||
const char compat[] = "sifive,test1\0sifive,test0\0syscon";
|
||||
qemu_fdt_setprop(fdt, nodename, "compatible", compat, sizeof(compat));
|
||||
qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat));
|
||||
}
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
||||
qemu_fdt_setprop_cells(fdt, name, "reg",
|
||||
0x0, memmap[VIRT_TEST].base,
|
||||
0x0, memmap[VIRT_TEST].size);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_phandle);
|
||||
test_phandle = qemu_fdt_get_phandle(fdt, nodename);
|
||||
g_free(nodename);
|
||||
qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle);
|
||||
test_phandle = qemu_fdt_get_phandle(fdt, name);
|
||||
g_free(name);
|
||||
|
||||
nodename = g_strdup_printf("/reboot");
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);
|
||||
g_free(nodename);
|
||||
name = g_strdup_printf("/soc/reboot");
|
||||
qemu_fdt_add_subnode(fdt, name);
|
||||
qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot");
|
||||
qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
|
||||
qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
|
||||
qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET);
|
||||
g_free(name);
|
||||
|
||||
nodename = g_strdup_printf("/poweroff");
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);
|
||||
g_free(nodename);
|
||||
name = g_strdup_printf("/soc/poweroff");
|
||||
qemu_fdt_add_subnode(fdt, name);
|
||||
qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff");
|
||||
qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
|
||||
qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
|
||||
qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS);
|
||||
g_free(name);
|
||||
|
||||
nodename = g_strdup_printf("/uart@%lx",
|
||||
(long)memmap[VIRT_UART0].base);
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
||||
name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
|
||||
qemu_fdt_add_subnode(fdt, name);
|
||||
qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
|
||||
qemu_fdt_setprop_cells(fdt, name, "reg",
|
||||
0x0, memmap[VIRT_UART0].base,
|
||||
0x0, memmap[VIRT_UART0].size);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ);
|
||||
qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400);
|
||||
qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
|
||||
qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ);
|
||||
|
||||
qemu_fdt_add_subnode(fdt, "/chosen");
|
||||
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
|
||||
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
|
||||
if (cmdline) {
|
||||
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
|
||||
}
|
||||
g_free(nodename);
|
||||
g_free(name);
|
||||
|
||||
nodename = g_strdup_printf("/rtc@%lx",
|
||||
(long)memmap[VIRT_RTC].base);
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible",
|
||||
"google,goldfish-rtc");
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
||||
name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
|
||||
qemu_fdt_add_subnode(fdt, name);
|
||||
qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc");
|
||||
qemu_fdt_setprop_cells(fdt, name, "reg",
|
||||
0x0, memmap[VIRT_RTC].base,
|
||||
0x0, memmap[VIRT_RTC].size);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", RTC_IRQ);
|
||||
g_free(nodename);
|
||||
qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
|
||||
qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ);
|
||||
g_free(name);
|
||||
|
||||
nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
|
||||
qemu_fdt_add_subnode(s->fdt, nodename);
|
||||
qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash");
|
||||
qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
|
||||
name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase);
|
||||
qemu_fdt_add_subnode(s->fdt, name);
|
||||
qemu_fdt_setprop_string(s->fdt, name, "compatible", "cfi-flash");
|
||||
qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
|
||||
2, flashbase, 2, flashsize,
|
||||
2, flashbase + flashsize, 2, flashsize);
|
||||
qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4);
|
||||
g_free(nodename);
|
||||
qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4);
|
||||
g_free(name);
|
||||
}
|
||||
|
||||
|
||||
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
|
||||
hwaddr ecam_base, hwaddr ecam_size,
|
||||
hwaddr mmio_base, hwaddr mmio_size,
|
||||
@ -475,22 +490,101 @@ static void virt_machine_init(MachineState *machine)
|
||||
MemoryRegion *system_memory = get_system_memory();
|
||||
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
|
||||
char *plic_hart_config;
|
||||
char *plic_hart_config, *soc_name;
|
||||
size_t plic_hart_config_len;
|
||||
target_ulong start_addr = memmap[VIRT_DRAM].base;
|
||||
uint32_t fdt_load_addr;
|
||||
uint64_t kernel_entry;
|
||||
int i;
|
||||
unsigned int smp_cpus = machine->smp.cpus;
|
||||
DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
|
||||
int i, j, base_hartid, hart_count;
|
||||
|
||||
/* Initialize SOC */
|
||||
object_initialize_child(OBJECT(machine), "soc", &s->soc,
|
||||
TYPE_RISCV_HART_ARRAY);
|
||||
object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
|
||||
&error_abort);
|
||||
object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
|
||||
&error_abort);
|
||||
sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
|
||||
/* Check socket count limit */
|
||||
if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
|
||||
error_report("number of sockets/nodes should be less than %d",
|
||||
VIRT_SOCKETS_MAX);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
/* Initialize sockets */
|
||||
mmio_plic = virtio_plic = pcie_plic = NULL;
|
||||
for (i = 0; i < riscv_socket_count(machine); i++) {
|
||||
if (!riscv_socket_check_hartids(machine, i)) {
|
||||
error_report("discontinuous hartids in socket%d", i);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
base_hartid = riscv_socket_first_hartid(machine, i);
|
||||
if (base_hartid < 0) {
|
||||
error_report("can't find hartid base for socket%d", i);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
hart_count = riscv_socket_hart_count(machine, i);
|
||||
if (hart_count < 0) {
|
||||
error_report("can't find hart count for socket%d", i);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
soc_name = g_strdup_printf("soc%d", i);
|
||||
object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
|
||||
TYPE_RISCV_HART_ARRAY);
|
||||
g_free(soc_name);
|
||||
object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
|
||||
machine->cpu_type, &error_abort);
|
||||
object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
|
||||
base_hartid, &error_abort);
|
||||
object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
|
||||
hart_count, &error_abort);
|
||||
sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
|
||||
|
||||
/* Per-socket CLINT */
|
||||
sifive_clint_create(
|
||||
memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
|
||||
memmap[VIRT_CLINT].size, base_hartid, hart_count,
|
||||
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
|
||||
|
||||
/* Per-socket PLIC hart topology configuration string */
|
||||
plic_hart_config_len =
|
||||
(strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count;
|
||||
plic_hart_config = g_malloc0(plic_hart_config_len);
|
||||
for (j = 0; j < hart_count; j++) {
|
||||
if (j != 0) {
|
||||
strncat(plic_hart_config, ",", plic_hart_config_len);
|
||||
}
|
||||
strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG,
|
||||
plic_hart_config_len);
|
||||
plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
|
||||
}
|
||||
|
||||
/* Per-socket PLIC */
|
||||
s->plic[i] = sifive_plic_create(
|
||||
memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size,
|
||||
plic_hart_config, base_hartid,
|
||||
VIRT_PLIC_NUM_SOURCES,
|
||||
VIRT_PLIC_NUM_PRIORITIES,
|
||||
VIRT_PLIC_PRIORITY_BASE,
|
||||
VIRT_PLIC_PENDING_BASE,
|
||||
VIRT_PLIC_ENABLE_BASE,
|
||||
VIRT_PLIC_ENABLE_STRIDE,
|
||||
VIRT_PLIC_CONTEXT_BASE,
|
||||
VIRT_PLIC_CONTEXT_STRIDE,
|
||||
memmap[VIRT_PLIC].size);
|
||||
g_free(plic_hart_config);
|
||||
|
||||
/* Try to use different PLIC instance based device type */
|
||||
if (i == 0) {
|
||||
mmio_plic = s->plic[i];
|
||||
virtio_plic = s->plic[i];
|
||||
pcie_plic = s->plic[i];
|
||||
}
|
||||
if (i == 1) {
|
||||
virtio_plic = s->plic[i];
|
||||
pcie_plic = s->plic[i];
|
||||
}
|
||||
if (i == 2) {
|
||||
pcie_plic = s->plic[i];
|
||||
}
|
||||
}
|
||||
|
||||
/* register system main memory (actual RAM) */
|
||||
memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
|
||||
@ -547,38 +641,14 @@ static void virt_machine_init(MachineState *machine)
|
||||
virt_memmap[VIRT_MROM].size, kernel_entry,
|
||||
fdt_load_addr, s->fdt);
|
||||
|
||||
/* create PLIC hart topology configuration string */
|
||||
plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
|
||||
plic_hart_config = g_malloc0(plic_hart_config_len);
|
||||
for (i = 0; i < smp_cpus; i++) {
|
||||
if (i != 0) {
|
||||
strncat(plic_hart_config, ",", plic_hart_config_len);
|
||||
}
|
||||
strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
|
||||
plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
|
||||
}
|
||||
|
||||
/* MMIO */
|
||||
s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
|
||||
plic_hart_config, 0,
|
||||
VIRT_PLIC_NUM_SOURCES,
|
||||
VIRT_PLIC_NUM_PRIORITIES,
|
||||
VIRT_PLIC_PRIORITY_BASE,
|
||||
VIRT_PLIC_PENDING_BASE,
|
||||
VIRT_PLIC_ENABLE_BASE,
|
||||
VIRT_PLIC_ENABLE_STRIDE,
|
||||
VIRT_PLIC_CONTEXT_BASE,
|
||||
VIRT_PLIC_CONTEXT_STRIDE,
|
||||
memmap[VIRT_PLIC].size);
|
||||
sifive_clint_create(memmap[VIRT_CLINT].base,
|
||||
memmap[VIRT_CLINT].size, 0, smp_cpus,
|
||||
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
|
||||
/* SiFive Test MMIO device */
|
||||
sifive_test_create(memmap[VIRT_TEST].base);
|
||||
|
||||
/* VirtIO MMIO devices */
|
||||
for (i = 0; i < VIRTIO_COUNT; i++) {
|
||||
sysbus_create_simple("virtio-mmio",
|
||||
memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
|
||||
qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
|
||||
qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
|
||||
}
|
||||
|
||||
gpex_pcie_init(system_memory,
|
||||
@ -587,14 +657,14 @@ static void virt_machine_init(MachineState *machine)
|
||||
memmap[VIRT_PCIE_MMIO].base,
|
||||
memmap[VIRT_PCIE_MMIO].size,
|
||||
memmap[VIRT_PCIE_PIO].base,
|
||||
DEVICE(s->plic), true);
|
||||
DEVICE(pcie_plic), true);
|
||||
|
||||
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
|
||||
0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
|
||||
0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
|
||||
serial_hd(0), DEVICE_LITTLE_ENDIAN);
|
||||
|
||||
sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
|
||||
qdev_get_gpio_in(DEVICE(s->plic), RTC_IRQ));
|
||||
qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
|
||||
|
||||
virt_flash_create(s);
|
||||
|
||||
@ -604,8 +674,6 @@ static void virt_machine_init(MachineState *machine)
|
||||
drive_get(IF_PFLASH, 0, i));
|
||||
}
|
||||
virt_flash_map(s, system_memory);
|
||||
|
||||
g_free(plic_hart_config);
|
||||
}
|
||||
|
||||
static void virt_machine_instance_init(Object *obj)
|
||||
@ -618,9 +686,13 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
|
||||
|
||||
mc->desc = "RISC-V VirtIO board";
|
||||
mc->init = virt_machine_init;
|
||||
mc->max_cpus = 8;
|
||||
mc->max_cpus = VIRT_CPUS_MAX;
|
||||
mc->default_cpu_type = VIRT_CPU;
|
||||
mc->pci_allow_0_address = true;
|
||||
mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
|
||||
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
|
||||
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
|
||||
mc->numa_mem_supported = true;
|
||||
}
|
||||
|
||||
static const TypeInfo virt_machine_typeinfo = {
|
||||
|
||||
@ -23,6 +23,9 @@
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/block/flash.h"
|
||||
|
||||
#define VIRT_CPUS_MAX 8
|
||||
#define VIRT_SOCKETS_MAX 8
|
||||
|
||||
#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
|
||||
#define RISCV_VIRT_MACHINE(obj) \
|
||||
OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE)
|
||||
@ -32,8 +35,8 @@ typedef struct {
|
||||
MachineState parent;
|
||||
|
||||
/*< public >*/
|
||||
RISCVHartArrayState soc;
|
||||
DeviceState *plic;
|
||||
RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
|
||||
DeviceState *plic[VIRT_SOCKETS_MAX];
|
||||
PFlashCFI01 *flash[2];
|
||||
|
||||
void *fdt;
|
||||
@ -74,6 +77,8 @@ enum {
|
||||
#define VIRT_PLIC_ENABLE_STRIDE 0x80
|
||||
#define VIRT_PLIC_CONTEXT_BASE 0x200000
|
||||
#define VIRT_PLIC_CONTEXT_STRIDE 0x1000
|
||||
#define VIRT_PLIC_SIZE(__num_context) \
|
||||
(VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
|
||||
|
||||
#define FDT_PCI_ADDR_CELLS 3
|
||||
#define FDT_PCI_INT_CELLS 1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user