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ARM postincrememnt addressing fix.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1970 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook 2006-06-14 14:36:07 +00:00
parent d1e42c5c1e
commit 191f9a93f4
1 changed files with 12 additions and 7 deletions
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19
target-arm/translate.c
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@ -383,19 +383,23 @@ static inline void gen_add_data_offset(DisasContext *s, unsigned int insn)
} }
} }
static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn) static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
int extra)
{ {
int val, rm; int val, rm;
if (insn & (1 << 22)) { if (insn & (1 << 22)) {
/* immediate */ /* immediate */
val = (insn & 0xf) | ((insn >> 4) & 0xf0); val = (insn & 0xf) | ((insn >> 4) & 0xf0);
val += extra;
if (!(insn & (1 << 23))) if (!(insn & (1 << 23)))
val = -val; val = -val;
if (val != 0) if (val != 0)
gen_op_addl_T1_im(val); gen_op_addl_T1_im(val);
} else { } else {
/* register */ /* register */
if (extra)
gen_op_addl_T1_im(extra);
rm = (insn) & 0xf; rm = (insn) & 0xf;
gen_movl_T2_reg(s, rm); gen_movl_T2_reg(s, rm);
if (!(insn & (1 << 23))) if (!(insn & (1 << 23)))
@ -1530,12 +1534,14 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
} }
} }
} else { } else {
int address_offset;
/* Misc load/store */ /* Misc load/store */
rn = (insn >> 16) & 0xf; rn = (insn >> 16) & 0xf;
rd = (insn >> 12) & 0xf; rd = (insn >> 12) & 0xf;
gen_movl_T1_reg(s, rn); gen_movl_T1_reg(s, rn);
if (insn & (1 << 24)) if (insn & (1 << 24))
gen_add_datah_offset(s, insn); gen_add_datah_offset(s, insn, 0);
address_offset = 0;
if (insn & (1 << 20)) { if (insn & (1 << 20)) {
/* load */ /* load */
switch(sh) { switch(sh) {
@ -1560,8 +1566,6 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
gen_op_addl_T1_im(4); gen_op_addl_T1_im(4);
gen_movl_T0_reg(s, rd + 1); gen_movl_T0_reg(s, rd + 1);
gen_ldst(stl, s); gen_ldst(stl, s);
if ((insn & (1 << 24)) || (insn & (1 << 20)))
gen_op_addl_T1_im(-4);
} else { } else {
/* load */ /* load */
gen_ldst(ldl, s); gen_ldst(ldl, s);
@ -1569,18 +1573,19 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
gen_op_addl_T1_im(4); gen_op_addl_T1_im(4);
gen_ldst(ldl, s); gen_ldst(ldl, s);
gen_movl_reg_T0(s, rd + 1); gen_movl_reg_T0(s, rd + 1);
if ((insn & (1 << 24)) || (insn & (1 << 20)))
gen_op_addl_T1_im(-4);
} }
address_offset = -4;
} else { } else {
/* store */ /* store */
gen_movl_T0_reg(s, rd); gen_movl_T0_reg(s, rd);
gen_ldst(stw, s); gen_ldst(stw, s);
} }
if (!(insn & (1 << 24))) { if (!(insn & (1 << 24))) {
gen_add_datah_offset(s, insn); gen_add_datah_offset(s, insn, address_offset);
gen_movl_reg_T1(s, rn); gen_movl_reg_T1(s, rn);
} else if (insn & (1 << 21)) { } else if (insn & (1 << 21)) {
if (address_offset)
gen_op_addl_T1_im(address_offset);
gen_movl_reg_T1(s, rn); gen_movl_reg_T1(s, rn);
} }
} }