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MIPS patches queue

Browse Source 
- Deprecate nanoMIPS ISA
 - Fix PageMask with variable page size (Huacai Chen)
 - Fix memory leak in boston_fdt_filter (Coverity CID 1432275, Peter Maydell)
 
 CI jobs results:
 . https://cirrus-ci.com/build/5439131968864256
 . https://gitlab.com/philmd/qemu/-/pipelines/213403385
 . https://travis-ci.org/github/philmd/qemu/builds/742312387
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAl+ogh8ACgkQ4+MsLN6t
 wN7Oww//aiMMMC472tbS9SwaBggw56F7IoizWXA5U2sPC5xcDPilQKyfP4FgtMmo
 pO9x61+0Vgel0eiR9npbjpdXeHOZTYWJmgMBOkrEd7O7b7VrJL94lFFjcGg+ysEg
 memWdhU1FFUChe4wMPplYww9G0fEINbqyucoSdI7llg7LWoTWbk4tlvJ88c/VyNM
 N4aEFAOq84Q5PeZ2X3CDvf3cxEKqaRWTsF/qnWKKZlcKRtANfT+gfW0PdRWDdgl/
 jKeVymU93RHkuI9qKGh3kWT+sWztHmydePuadwaOSR1svrnf1kCeh+qsh7l6z5Fc
 +eP2zXeDxmdEe/CpsAtuhBecsSiO/exKNO8h9Fy1TxdwwHHV+rdAh1NYvqlJfzki
 YmvM+W8x0IOJB6RjCRfdF2SZkvzBDaWLZYDe97EdXQ6XsG6nmHuSRT99PoLetYvw
 zeVWKD4wzR79b4GglWkScXHGy0jRpEeU0A3EM29nn/mqaEPEzU41+G1IKbqs7qWJ
 mbkARmqRG/0ytGrtIQ2i11WAIt2+zseXTR2aJE6tpT978Iq3aLhEVUBvDr4pkbfa
 +L0nVcLdkn+qIRsOWYwj6KwES8FrZGFCBWKNk736Gylyt1D7twj9hF5Eyb8kY9wk
 tfy77Kudwc/JlG3iujLrnRa8UrHf3cqLys0t8jrSuIJWBU9BtKo=
 =pdix
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-fixes-20201109' into staging

MIPS patches queue

- Deprecate nanoMIPS ISA
- Fix PageMask with variable page size (Huacai Chen)
- Fix memory leak in boston_fdt_filter (Coverity CID 1432275, Peter Maydell)

CI jobs results:
. https://cirrus-ci.com/build/5439131968864256
. https://gitlab.com/philmd/qemu/-/pipelines/213403385
. https://travis-ci.org/github/philmd/qemu/builds/742312387

# gpg: Signature made Sun 08 Nov 2020 23:41:19 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd-gitlab/tags/mips-fixes-20201109:
  hw/mips/boston: Fix memory leak in boston_fdt_filter() error-handling paths
  target/mips: Fix PageMask with variable page size
  target/mips: Deprecate nanoMIPS ISA

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-11-09 10:10:49 +00:00
commit 193f51ddcf
5 changed files with 54 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
View File

@ -227,7 +227,7 @@ R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Odd Fixes
F: target/mips/
F: default-configs/*mips*
F: disas/*mips*
F: disas/mips.c
F: docs/system/cpu-models-mips.rst.inc
F: hw/intc/mips_gic.c
F: hw/mips/
@ -240,6 +240,10 @@ F: include/hw/timer/mips_gictimer.h
F: tests/tcg/mips/
K: ^Subject:.*(?i)mips
MIPS TCG CPUs (nanoMIPS ISA)
S: Orphan
F: disas/nanomips.*
Moxie TCG CPUs
M: Anthony Green <green@moxielogic.com>
S: Maintained

23
docs/system/deprecated.rst
View File

@ -310,6 +310,13 @@ to build binaries for it.
``Icelake-Client`` CPU Models are deprecated. Use ``Icelake-Server`` CPU
Models instead.
MIPS ``I7200`` CPU Model (since 5.2)
''''''''''''''''''''''''''''''''''''
The ``I7200`` guest CPU relies on the nanoMIPS ISA, which is deprecated
(the ISA has never been upstreamed to a compiler toolchain). Therefore
this CPU is also deprecated.
System emulator devices
-----------------------
@ -407,6 +414,13 @@ The ``ppc64abi32`` architecture has a number of issues which regularly
trip up our CI testing and is suspected to be quite broken. For that
reason the maintainers strongly suspect no one actually uses it.
MIPS ``I7200`` CPU (since 5.2)
''''''''''''''''''''''''''''''
The ``I7200`` guest CPU relies on the nanoMIPS ISA, which is deprecated
(the ISA has never been upstreamed to a compiler toolchain). Therefore
this CPU is also deprecated.
Related binaries
----------------
@ -471,6 +485,15 @@ versions, aliases will point to newer CPU model versions
depending on the machine type, so management software must
resolve CPU model aliases before starting a virtual machine.
Guest Emulator ISAs
-------------------
nanoMIPS ISA
''''''''''''
The ``nanoMIPS`` ISA has never been upstreamed to any compiler toolchain.
As it is hard to generate binaries for it, declare it deprecated.
Recently removed features
=========================

10
hw/mips/boston.c
View File

@ -349,11 +349,9 @@ static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
MachineState *machine = s->mach;
const char *cmdline;
int err;
void *fdt;
size_t fdt_sz, ram_low_sz, ram_high_sz;
fdt_sz = fdt_totalsize(fdt_orig) * 2;
fdt = g_malloc0(fdt_sz);
size_t ram_low_sz, ram_high_sz;
size_t fdt_sz = fdt_totalsize(fdt_orig) * 2;
g_autofree void *fdt = g_malloc0(fdt_sz);
err = fdt_open_into(fdt_orig, fdt, fdt_sz);
if (err) {
@ -380,7 +378,7 @@ static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
s->fdt_base = *load_addr;
return fdt;
return g_steal_pointer(&fdt);
}
static const void *boston_kernel_filter(void *opaque, const void *kernel,

27
target/mips/cp0_helper.c
View File

@ -892,13 +892,28 @@ void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1)
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
{
uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
(mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
uint32_t mask;
int maskbits;
/* Don't care MASKX as we don't support 1KB page */
mask = extract32((uint32_t)arg1, CP0PM_MASK, 16);
maskbits = cto32(mask);
/* Ensure no more set bit after first zero */
if ((mask >> maskbits) != 0) {
goto invalid;
}
/* We don't support VTLB entry smaller than target page */
if ((maskbits + 12) < TARGET_PAGE_BITS) {
goto invalid;
}
env->CP0_PageMask = mask << CP0PM_MASK;
return;
invalid:
/* When invalid, set to default target page size. */
env->CP0_PageMask = (~TARGET_PAGE_MASK >> 12) << CP0PM_MASK;
}
void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)

1
target/mips/cpu.h
View File

@ -619,6 +619,7 @@ struct CPUMIPSState {
* CP0 Register 5
*/
int32_t CP0_PageMask;
#define CP0PM_MASK 13
int32_t CP0_PageGrain_rw_bitmask;
int32_t CP0_PageGrain;
#define CP0PG_RIE 31