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target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns

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Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-8-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2022-01-18 09:45:10 +08:00 committed by Alistair Francis
parent 40d78c85f6
commit 193fb5c9bd
1 changed files with 2 additions and 1 deletions
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3
target/riscv/insn_trans/trans_rvv.c.inc
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@ -2937,7 +2937,8 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
static bool freduction_check(DisasContext *s, arg_rmrr *a)
{
return reduction_check(s, a) &&
require_rvf(s);
require_rvf(s) &&
require_zve64f(s);
}
GEN_OPFVV_TRANS(vfredsum_vs, freduction_check)