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xhci: kill xhci_mem_{read,write} dispatcher functions
... and register subregions instead, so we offload the dispatching to the the memory subsystem which is designed to handle it. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Gerd Hoffmann
parent
fa8ee89e8b
commit
1b067564ce
@ -404,6 +404,10 @@ struct XHCIState {
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USBBus bus;
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qemu_irq irq;
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MemoryRegion mem;
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MemoryRegion mem_cap;
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MemoryRegion mem_oper;
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MemoryRegion mem_runtime;
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MemoryRegion mem_doorbell;
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const char *name;
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unsigned int devaddr;
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@ -2343,8 +2347,9 @@ static void xhci_reset(DeviceState *dev)
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xhci_mfwrap_update(xhci);
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}
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static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
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static uint64_t xhci_cap_read(void *ptr, target_phys_addr_t reg, unsigned size)
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{
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XHCIState *xhci = ptr;
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uint32_t ret;
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switch (reg) {
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@ -2401,7 +2406,7 @@ static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
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ret = 0x00000000; /* reserved */
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break;
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default:
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fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", reg);
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fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", (int)reg);
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ret = 0;
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}
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@ -2482,8 +2487,9 @@ static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val)
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}
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}
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static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
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static uint64_t xhci_oper_read(void *ptr, target_phys_addr_t reg, unsigned size)
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{
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XHCIState *xhci = ptr;
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uint32_t ret;
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if (reg >= 0x400) {
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@ -2519,7 +2525,7 @@ static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
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ret = xhci->config;
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break;
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default:
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fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", reg);
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fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", (int)reg);
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ret = 0;
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}
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@ -2527,8 +2533,11 @@ static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
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return ret;
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}
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static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val)
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static void xhci_oper_write(void *ptr, target_phys_addr_t reg,
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uint64_t val, unsigned size)
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{
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XHCIState *xhci = ptr;
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if (reg >= 0x400) {
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xhci_port_write(xhci, reg - 0x400, val);
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return;
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@ -2586,12 +2595,14 @@ static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val)
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xhci->config = val & 0xff;
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break;
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default:
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fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
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fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg);
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}
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}
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static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
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static uint64_t xhci_runtime_read(void *ptr, target_phys_addr_t reg,
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unsigned size)
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{
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XHCIState *xhci = ptr;
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uint32_t ret = 0;
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if (reg < 0x20) {
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@ -2600,7 +2611,8 @@ static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
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ret = xhci_mfindex_get(xhci) & 0x3fff;
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break;
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default:
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fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", reg);
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fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n",
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(int)reg);
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break;
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}
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} else {
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@ -2635,14 +2647,16 @@ static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
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return ret;
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}
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static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val)
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static void xhci_runtime_write(void *ptr, target_phys_addr_t reg,
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uint64_t val, unsigned size)
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{
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XHCIState *xhci = ptr;
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int v = (reg - 0x20) / 0x20;
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XHCIInterrupter *intr = &xhci->intr[v];
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trace_usb_xhci_runtime_write(reg, val);
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if (reg < 0x20) {
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fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
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fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg);
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return;
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}
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@ -2684,19 +2698,24 @@ static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val)
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xhci_events_update(xhci, v);
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break;
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default:
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fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
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fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n",
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(int)reg);
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}
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}
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static uint32_t xhci_doorbell_read(XHCIState *xhci, uint32_t reg)
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static uint64_t xhci_doorbell_read(void *ptr, target_phys_addr_t reg,
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unsigned size)
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{
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/* doorbells always read as 0 */
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trace_usb_xhci_doorbell_read(reg, 0);
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return 0;
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}
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static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val)
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static void xhci_doorbell_write(void *ptr, target_phys_addr_t reg,
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uint64_t val, unsigned size)
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{
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XHCIState *xhci = ptr;
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trace_usb_xhci_doorbell_write(reg, val);
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if (!xhci_running(xhci)) {
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@ -2710,69 +2729,47 @@ static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val)
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if (val == 0) {
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xhci_process_commands(xhci);
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} else {
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fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", val);
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fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n",
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(uint32_t)val);
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}
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} else {
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if (reg > MAXSLOTS) {
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fprintf(stderr, "xhci: bad doorbell %d\n", reg);
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fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg);
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} else if (val > 31) {
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fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", reg, val);
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fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n",
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(int)reg, (uint32_t)val);
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} else {
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xhci_kick_ep(xhci, reg, val);
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}
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}
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}
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static uint64_t xhci_mem_read(void *ptr, target_phys_addr_t addr,
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unsigned size)
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{
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XHCIState *xhci = ptr;
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static const MemoryRegionOps xhci_cap_ops = {
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.read = xhci_cap_read,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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/* Only aligned reads are allowed on xHCI */
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if (addr & 3) {
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fprintf(stderr, "xhci_mem_read: Mis-aligned read\n");
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return 0;
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}
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static const MemoryRegionOps xhci_oper_ops = {
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.read = xhci_oper_read,
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.write = xhci_oper_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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if (addr < LEN_CAP) {
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return xhci_cap_read(xhci, addr);
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} else if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
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return xhci_oper_read(xhci, addr - OFF_OPER);
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} else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
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return xhci_runtime_read(xhci, addr - OFF_RUNTIME);
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} else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
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return xhci_doorbell_read(xhci, addr - OFF_DOORBELL);
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} else {
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fprintf(stderr, "xhci_mem_read: Bad offset %x\n", (int)addr);
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return 0;
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}
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}
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static const MemoryRegionOps xhci_runtime_ops = {
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.read = xhci_runtime_read,
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.write = xhci_runtime_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void xhci_mem_write(void *ptr, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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XHCIState *xhci = ptr;
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/* Only aligned writes are allowed on xHCI */
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if (addr & 3) {
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fprintf(stderr, "xhci_mem_write: Mis-aligned write\n");
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return;
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}
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if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
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xhci_oper_write(xhci, addr - OFF_OPER, val);
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} else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
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xhci_runtime_write(xhci, addr - OFF_RUNTIME, val);
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} else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
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xhci_doorbell_write(xhci, addr - OFF_DOORBELL, val);
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} else {
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fprintf(stderr, "xhci_mem_write: Bad offset %x\n", (int)addr);
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}
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}
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static const MemoryRegionOps xhci_mem_ops = {
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.read = xhci_mem_read,
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.write = xhci_mem_write,
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static const MemoryRegionOps xhci_doorbell_ops = {
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.read = xhci_doorbell_read,
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.write = xhci_doorbell_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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@ -2938,8 +2935,21 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
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xhci->irq = xhci->pci_dev.irq[0];
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memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci,
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"xhci", LEN_REGS);
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memory_region_init(&xhci->mem, "xhci", LEN_REGS);
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memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci,
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"capabilities", LEN_CAP);
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memory_region_init_io(&xhci->mem_oper, &xhci_oper_ops, xhci,
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"operational", 0x400 + 0x10 * xhci->numports);
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memory_region_init_io(&xhci->mem_runtime, &xhci_runtime_ops, xhci,
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"runtime", LEN_RUNTIME);
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memory_region_init_io(&xhci->mem_doorbell, &xhci_doorbell_ops, xhci,
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"doorbell", LEN_DOORBELL);
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memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
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memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
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memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
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memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
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pci_register_bar(&xhci->pci_dev, 0,
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PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
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&xhci->mem);
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