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target-alpha: use the new TCG logical operations
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5502 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -940,12 +940,8 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
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if (ra != 31) {
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if (islit)
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tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
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else {
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TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
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tcg_gen_not_i64(tmp, cpu_ir[rb]);
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tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], tmp);
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tcg_temp_free(tmp);
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}
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else
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tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
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} else
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tcg_gen_movi_i64(cpu_ir[rc], 0);
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}
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@ -988,12 +984,8 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
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if (ra != 31) {
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if (islit)
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tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
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else {
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TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
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tcg_gen_not_i64(tmp, cpu_ir[rb]);
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tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], tmp);
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tcg_temp_free(tmp);
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}
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else
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tcg_gen_orc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
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} else {
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if (islit)
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tcg_gen_movi_i64(cpu_ir[rc], ~lit);
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@ -1032,12 +1024,8 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
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if (ra != 31) {
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if (islit)
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tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
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else {
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TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
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tcg_gen_not_i64(tmp, cpu_ir[rb]);
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tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], tmp);
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tcg_temp_free(tmp);
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}
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else
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tcg_gen_eqv_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
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} else {
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if (islit)
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tcg_gen_movi_i64(cpu_ir[rc], ~lit);
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