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target/riscv: Only flush TLB if SATP.ASID changes

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There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857

Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Jonathan Behrens 2019-05-08 13:38:35 -04:00 committed by Palmer Dabbelt
parent 087b051a51
commit 1e0d985fa9
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1 changed files with 3 additions and 1 deletions
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4
target/riscv/csr.c
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@ -723,7 +723,9 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -1;
} else {
tlb_flush(CPU(riscv_env_get_cpu(env)));
if((val ^ env->satp) & SATP_ASID) {
tlb_flush(CPU(riscv_env_get_cpu(env)));
}
env->satp = val;
}
}