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hw/armv7m_nvic: Make the NVIC a freestanding class
Rearrange the GIC and NVIC so both are straightforward subclasses of a common class, rather than having the NVIC source file textually include arm_gic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
parent
2b518c56a6
commit
1e8cae4dfe
@ -6,7 +6,7 @@ obj-y += cadence_uart.o
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obj-y += cadence_ttc.o
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obj-y += cadence_gem.o
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obj-y += xilinx_zynq.o zynq_slcr.o
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obj-y += arm_gic.o
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obj-y += arm_gic.o arm_gic_common.o
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obj-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
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obj-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
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obj-y += exynos4_boards.o exynos4210_uart.o exynos4210_pwm.o
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241
hw/arm_gic.c
241
hw/arm_gic.c
@ -19,13 +19,7 @@
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*/
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#include "sysbus.h"
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/* Maximum number of possible interrupts, determined by the GIC architecture */
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#define GIC_MAXIRQ 1020
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/* First 32 are private to each CPU (SGIs and PPIs). */
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#define GIC_INTERNAL 32
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/* Maximum number of possible CPU interfaces, determined by GIC architecture */
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#define NCPU 8
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#include "arm_gic_internal.h"
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//#define DEBUG_GIC
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@ -36,88 +30,12 @@ do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0)
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#define DPRINTF(fmt, ...) do {} while(0)
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#endif
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/* The NVIC has 16 internal vectors. However these are not exposed
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through the normal GIC interface. */
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#define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0)
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static const uint8_t gic_id[] = {
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0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
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};
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#define FROM_SYSBUSGIC(type, dev) \
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DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev))
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typedef struct gic_irq_state
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{
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/* The enable bits are only banked for per-cpu interrupts. */
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unsigned enabled:NCPU;
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unsigned pending:NCPU;
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unsigned active:NCPU;
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unsigned level:NCPU;
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unsigned model:1; /* 0 = N:N, 1 = 1:N */
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unsigned trigger:1; /* nonzero = edge triggered. */
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} gic_irq_state;
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#define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1)))
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#define NUM_CPU(s) ((s)->num_cpu)
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#define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
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#define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
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#define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
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#define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
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#define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
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#define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
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#define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
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#define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
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#define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
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#define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
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#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
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#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
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#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
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#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
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#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
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#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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#define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
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s->priority1[irq][cpu] : \
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s->priority2[(irq) - GIC_INTERNAL])
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#define GIC_TARGET(irq) s->irq_target[irq]
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typedef struct gic_state
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{
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SysBusDevice busdev;
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qemu_irq parent_irq[NCPU];
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int enabled;
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int cpu_enabled[NCPU];
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gic_irq_state irq_state[GIC_MAXIRQ];
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int irq_target[GIC_MAXIRQ];
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int priority1[GIC_INTERNAL][NCPU];
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int priority2[GIC_MAXIRQ - GIC_INTERNAL];
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int last_active[GIC_MAXIRQ][NCPU];
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int priority_mask[NCPU];
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int running_irq[NCPU];
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int running_priority[NCPU];
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int current_pending[NCPU];
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uint32_t num_cpu;
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MemoryRegion iomem; /* Distributor */
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/* This is just so we can have an opaque pointer which identifies
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* both this GIC and which CPU interface we should be accessing.
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*/
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struct gic_state *backref[NCPU];
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MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */
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uint32_t num_irq;
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uint32_t revision;
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} gic_state;
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/* The special cases for the revision property: */
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#define REV_11MPCORE 0
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#define REV_NVIC 0xffffffff
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static inline int gic_get_current_cpu(gic_state *s)
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{
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if (s->num_cpu > 1) {
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@ -128,7 +46,7 @@ static inline int gic_get_current_cpu(gic_state *s)
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/* TODO: Many places that call this routine could be optimized. */
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/* Update interrupt status after enabled or pending bits have been changed. */
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static void gic_update(gic_state *s)
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void gic_update(gic_state *s)
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{
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int best_irq;
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int best_prio;
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@ -166,8 +84,7 @@ static void gic_update(gic_state *s)
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}
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}
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#ifdef NVIC
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static void gic_set_pending_private(gic_state *s, int cpu, int irq)
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void gic_set_pending_private(gic_state *s, int cpu, int irq)
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{
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int cm = 1 << cpu;
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@ -178,7 +95,6 @@ static void gic_set_pending_private(gic_state *s, int cpu, int irq)
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GIC_SET_PENDING(irq, cm);
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gic_update(s);
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}
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#endif
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/* Process a change in an external IRQ input. */
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static void gic_set_irq(void *opaque, int irq, int level)
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@ -232,7 +148,7 @@ static void gic_set_running_irq(gic_state *s, int cpu, int irq)
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gic_update(s);
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}
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static uint32_t gic_acknowledge_irq(gic_state *s, int cpu)
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uint32_t gic_acknowledge_irq(gic_state *s, int cpu)
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{
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int new_irq;
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int cm = 1 << cpu;
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@ -251,7 +167,7 @@ static uint32_t gic_acknowledge_irq(gic_state *s, int cpu)
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return new_irq;
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}
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static void gic_complete_irq(gic_state * s, int cpu, int irq)
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void gic_complete_irq(gic_state *s, int cpu, int irq)
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{
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int update = 0;
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int cm = 1 << cpu;
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@ -623,7 +539,6 @@ static const MemoryRegionOps gic_dist_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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#ifndef NVIC
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static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset)
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{
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switch (offset) {
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@ -715,125 +630,11 @@ static const MemoryRegionOps gic_cpu_ops = {
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.write = gic_do_cpu_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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#endif
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static void gic_reset(DeviceState *dev)
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{
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gic_state *s = FROM_SYSBUS(gic_state, sysbus_from_qdev(dev));
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int i;
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memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
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for (i = 0 ; i < NUM_CPU(s); i++) {
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s->priority_mask[i] = 0xf0;
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s->current_pending[i] = 1023;
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s->running_irq[i] = 1023;
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s->running_priority[i] = 0x100;
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s->cpu_enabled[i] = 0;
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}
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for (i = 0; i < 16; i++) {
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GIC_SET_ENABLED(i, ALL_CPU_MASK);
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GIC_SET_TRIGGER(i);
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}
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if (s->num_cpu == 1) {
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/* For uniprocessor GICs all interrupts always target the sole CPU */
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for (i = 0; i < GIC_MAXIRQ; i++) {
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s->irq_target[i] = 1;
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}
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}
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s->enabled = 0;
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}
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static void gic_save(QEMUFile *f, void *opaque)
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{
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gic_state *s = (gic_state *)opaque;
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int i;
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int j;
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qemu_put_be32(f, s->enabled);
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for (i = 0; i < NUM_CPU(s); i++) {
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qemu_put_be32(f, s->cpu_enabled[i]);
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for (j = 0; j < GIC_INTERNAL; j++)
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qemu_put_be32(f, s->priority1[j][i]);
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for (j = 0; j < s->num_irq; j++)
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qemu_put_be32(f, s->last_active[j][i]);
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qemu_put_be32(f, s->priority_mask[i]);
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qemu_put_be32(f, s->running_irq[i]);
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qemu_put_be32(f, s->running_priority[i]);
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qemu_put_be32(f, s->current_pending[i]);
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}
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for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
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qemu_put_be32(f, s->priority2[i]);
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}
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for (i = 0; i < s->num_irq; i++) {
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qemu_put_be32(f, s->irq_target[i]);
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qemu_put_byte(f, s->irq_state[i].enabled);
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qemu_put_byte(f, s->irq_state[i].pending);
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qemu_put_byte(f, s->irq_state[i].active);
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qemu_put_byte(f, s->irq_state[i].level);
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qemu_put_byte(f, s->irq_state[i].model);
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qemu_put_byte(f, s->irq_state[i].trigger);
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}
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}
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static int gic_load(QEMUFile *f, void *opaque, int version_id)
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{
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gic_state *s = (gic_state *)opaque;
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int i;
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int j;
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if (version_id != 3) {
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return -EINVAL;
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}
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s->enabled = qemu_get_be32(f);
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for (i = 0; i < NUM_CPU(s); i++) {
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s->cpu_enabled[i] = qemu_get_be32(f);
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for (j = 0; j < GIC_INTERNAL; j++)
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s->priority1[j][i] = qemu_get_be32(f);
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for (j = 0; j < s->num_irq; j++)
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s->last_active[j][i] = qemu_get_be32(f);
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s->priority_mask[i] = qemu_get_be32(f);
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s->running_irq[i] = qemu_get_be32(f);
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s->running_priority[i] = qemu_get_be32(f);
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s->current_pending[i] = qemu_get_be32(f);
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}
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for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
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s->priority2[i] = qemu_get_be32(f);
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}
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for (i = 0; i < s->num_irq; i++) {
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s->irq_target[i] = qemu_get_be32(f);
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s->irq_state[i].enabled = qemu_get_byte(f);
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s->irq_state[i].pending = qemu_get_byte(f);
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s->irq_state[i].active = qemu_get_byte(f);
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s->irq_state[i].level = qemu_get_byte(f);
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s->irq_state[i].model = qemu_get_byte(f);
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s->irq_state[i].trigger = qemu_get_byte(f);
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}
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return 0;
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}
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static void gic_init_irqs_and_distributor(gic_state *s, int num_irq)
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void gic_init_irqs_and_distributor(gic_state *s, int num_irq)
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{
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int i;
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if (s->num_cpu > NCPU) {
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hw_error("requested %u CPUs exceeds GIC maximum %d\n",
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s->num_cpu, NCPU);
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}
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s->num_irq = num_irq + GIC_BASE_IRQ;
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if (s->num_irq > GIC_MAXIRQ) {
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hw_error("requested %u interrupt lines exceeds GIC maximum %d\n",
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num_irq, GIC_MAXIRQ);
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}
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/* ITLinesNumber is represented as (N / 32) - 1 (see
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* gic_dist_readb) so this is an implementation imposed
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* restriction, not an architectural one:
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*/
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if (s->num_irq < 32 || (s->num_irq % 32)) {
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hw_error("%d interrupt lines unsupported: not divisible by 32\n",
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num_irq);
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}
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i = s->num_irq - GIC_INTERNAL;
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/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
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* GPIO array layout is thus:
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@ -850,17 +651,17 @@ static void gic_init_irqs_and_distributor(gic_state *s, int num_irq)
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sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
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}
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memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);
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register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s);
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}
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#ifndef NVIC
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static int arm_gic_init(SysBusDevice *dev)
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{
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/* Device instance init function for the GIC sysbus device */
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int i;
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gic_state *s = FROM_SYSBUS(gic_state, dev);
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ARMGICClass *agc = ARM_GIC_GET_CLASS(s);
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agc->parent_init(dev);
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gic_init_irqs_and_distributor(s, s->num_irq);
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/* Memory regions for the CPU interfaces (NVIC doesn't have these):
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@ -878,7 +679,6 @@ static int arm_gic_init(SysBusDevice *dev)
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memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i],
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"gic_cpu", 0x100);
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}
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/* Distributor */
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sysbus_init_mmio(dev, &s->iomem);
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/* cpu interfaces (one for "current cpu" plus one per cpu) */
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@ -888,30 +688,19 @@ static int arm_gic_init(SysBusDevice *dev)
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return 0;
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}
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static Property arm_gic_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1),
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DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32),
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/* Revision can be 1 or 2 for GIC architecture specification
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* versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
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* (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
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*/
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DEFINE_PROP_UINT32("revision", gic_state, revision, 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void arm_gic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
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ARMGICClass *agc = ARM_GIC_CLASS(klass);
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agc->parent_init = sbc->init;
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sbc->init = arm_gic_init;
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dc->props = arm_gic_properties;
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dc->reset = gic_reset;
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dc->no_user = 1;
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}
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static TypeInfo arm_gic_info = {
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.name = "arm_gic",
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.parent = TYPE_SYS_BUS_DEVICE,
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.name = TYPE_ARM_GIC,
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.parent = TYPE_ARM_GIC_COMMON,
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.instance_size = sizeof(gic_state),
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.class_init = arm_gic_class_init,
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};
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@ -922,5 +711,3 @@ static void arm_gic_register_types(void)
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}
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type_init(arm_gic_register_types)
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#endif
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184
hw/arm_gic_common.c
Normal file
184
hw/arm_gic_common.c
Normal file
@ -0,0 +1,184 @@
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/*
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* ARM GIC support - common bits of emulated and KVM kernel model
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*
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* Copyright (c) 2012 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "arm_gic_internal.h"
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static void gic_save(QEMUFile *f, void *opaque)
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{
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gic_state *s = (gic_state *)opaque;
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int i;
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int j;
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qemu_put_be32(f, s->enabled);
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for (i = 0; i < s->num_cpu; i++) {
|
||||
qemu_put_be32(f, s->cpu_enabled[i]);
|
||||
for (j = 0; j < GIC_INTERNAL; j++) {
|
||||
qemu_put_be32(f, s->priority1[j][i]);
|
||||
}
|
||||
for (j = 0; j < s->num_irq; j++) {
|
||||
qemu_put_be32(f, s->last_active[j][i]);
|
||||
}
|
||||
qemu_put_be32(f, s->priority_mask[i]);
|
||||
qemu_put_be32(f, s->running_irq[i]);
|
||||
qemu_put_be32(f, s->running_priority[i]);
|
||||
qemu_put_be32(f, s->current_pending[i]);
|
||||
}
|
||||
for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
|
||||
qemu_put_be32(f, s->priority2[i]);
|
||||
}
|
||||
for (i = 0; i < s->num_irq; i++) {
|
||||
qemu_put_be32(f, s->irq_target[i]);
|
||||
qemu_put_byte(f, s->irq_state[i].enabled);
|
||||
qemu_put_byte(f, s->irq_state[i].pending);
|
||||
qemu_put_byte(f, s->irq_state[i].active);
|
||||
qemu_put_byte(f, s->irq_state[i].level);
|
||||
qemu_put_byte(f, s->irq_state[i].model);
|
||||
qemu_put_byte(f, s->irq_state[i].trigger);
|
||||
}
|
||||
}
|
||||
|
||||
static int gic_load(QEMUFile *f, void *opaque, int version_id)
|
||||
{
|
||||
gic_state *s = (gic_state *)opaque;
|
||||
int i;
|
||||
int j;
|
||||
|
||||
if (version_id != 3) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
s->enabled = qemu_get_be32(f);
|
||||
for (i = 0; i < s->num_cpu; i++) {
|
||||
s->cpu_enabled[i] = qemu_get_be32(f);
|
||||
for (j = 0; j < GIC_INTERNAL; j++) {
|
||||
s->priority1[j][i] = qemu_get_be32(f);
|
||||
}
|
||||
for (j = 0; j < s->num_irq; j++) {
|
||||
s->last_active[j][i] = qemu_get_be32(f);
|
||||
}
|
||||
s->priority_mask[i] = qemu_get_be32(f);
|
||||
s->running_irq[i] = qemu_get_be32(f);
|
||||
s->running_priority[i] = qemu_get_be32(f);
|
||||
s->current_pending[i] = qemu_get_be32(f);
|
||||
}
|
||||
for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
|
||||
s->priority2[i] = qemu_get_be32(f);
|
||||
}
|
||||
for (i = 0; i < s->num_irq; i++) {
|
||||
s->irq_target[i] = qemu_get_be32(f);
|
||||
s->irq_state[i].enabled = qemu_get_byte(f);
|
||||
s->irq_state[i].pending = qemu_get_byte(f);
|
||||
s->irq_state[i].active = qemu_get_byte(f);
|
||||
s->irq_state[i].level = qemu_get_byte(f);
|
||||
s->irq_state[i].model = qemu_get_byte(f);
|
||||
s->irq_state[i].trigger = qemu_get_byte(f);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int arm_gic_common_init(SysBusDevice *dev)
|
||||
{
|
||||
gic_state *s = FROM_SYSBUS(gic_state, dev);
|
||||
int num_irq = s->num_irq;
|
||||
|
||||
if (s->num_cpu > NCPU) {
|
||||
hw_error("requested %u CPUs exceeds GIC maximum %d\n",
|
||||
s->num_cpu, NCPU);
|
||||
}
|
||||
s->num_irq += GIC_BASE_IRQ;
|
||||
if (s->num_irq > GIC_MAXIRQ) {
|
||||
hw_error("requested %u interrupt lines exceeds GIC maximum %d\n",
|
||||
num_irq, GIC_MAXIRQ);
|
||||
}
|
||||
/* ITLinesNumber is represented as (N / 32) - 1 (see
|
||||
* gic_dist_readb) so this is an implementation imposed
|
||||
* restriction, not an architectural one:
|
||||
*/
|
||||
if (s->num_irq < 32 || (s->num_irq % 32)) {
|
||||
hw_error("%d interrupt lines unsupported: not divisible by 32\n",
|
||||
num_irq);
|
||||
}
|
||||
|
||||
register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void arm_gic_common_reset(DeviceState *dev)
|
||||
{
|
||||
gic_state *s = FROM_SYSBUS(gic_state, sysbus_from_qdev(dev));
|
||||
int i;
|
||||
memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
|
||||
for (i = 0 ; i < s->num_cpu; i++) {
|
||||
s->priority_mask[i] = 0xf0;
|
||||
s->current_pending[i] = 1023;
|
||||
s->running_irq[i] = 1023;
|
||||
s->running_priority[i] = 0x100;
|
||||
s->cpu_enabled[i] = 0;
|
||||
}
|
||||
for (i = 0; i < 16; i++) {
|
||||
GIC_SET_ENABLED(i, ALL_CPU_MASK);
|
||||
GIC_SET_TRIGGER(i);
|
||||
}
|
||||
if (s->num_cpu == 1) {
|
||||
/* For uniprocessor GICs all interrupts always target the sole CPU */
|
||||
for (i = 0; i < GIC_MAXIRQ; i++) {
|
||||
s->irq_target[i] = 1;
|
||||
}
|
||||
}
|
||||
s->enabled = 0;
|
||||
}
|
||||
|
||||
static Property arm_gic_common_properties[] = {
|
||||
DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1),
|
||||
DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32),
|
||||
/* Revision can be 1 or 2 for GIC architecture specification
|
||||
* versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
|
||||
* (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
|
||||
*/
|
||||
DEFINE_PROP_UINT32("revision", gic_state, revision, 1),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void arm_gic_common_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
dc->reset = arm_gic_common_reset;
|
||||
dc->props = arm_gic_common_properties;
|
||||
dc->no_user = 1;
|
||||
sc->init = arm_gic_common_init;
|
||||
}
|
||||
|
||||
static TypeInfo arm_gic_common_type = {
|
||||
.name = TYPE_ARM_GIC_COMMON,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(gic_state),
|
||||
.class_size = sizeof(ARMGICCommonClass),
|
||||
.class_init = arm_gic_common_class_init,
|
||||
.abstract = true,
|
||||
};
|
||||
|
||||
static void register_types(void)
|
||||
{
|
||||
type_register_static(&arm_gic_common_type);
|
||||
}
|
||||
|
||||
type_init(register_types)
|
||||
136
hw/arm_gic_internal.h
Normal file
136
hw/arm_gic_internal.h
Normal file
@ -0,0 +1,136 @@
|
||||
/*
|
||||
* ARM GIC support - internal interfaces
|
||||
*
|
||||
* Copyright (c) 2012 Linaro Limited
|
||||
* Written by Peter Maydell
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef QEMU_ARM_GIC_INTERNAL_H
|
||||
#define QEMU_ARM_GIC_INTERNAL_H
|
||||
|
||||
#include "sysbus.h"
|
||||
|
||||
/* Maximum number of possible interrupts, determined by the GIC architecture */
|
||||
#define GIC_MAXIRQ 1020
|
||||
/* First 32 are private to each CPU (SGIs and PPIs). */
|
||||
#define GIC_INTERNAL 32
|
||||
/* Maximum number of possible CPU interfaces, determined by GIC architecture */
|
||||
#define NCPU 8
|
||||
|
||||
#define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1)))
|
||||
|
||||
/* The NVIC has 16 internal vectors. However these are not exposed
|
||||
through the normal GIC interface. */
|
||||
#define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0)
|
||||
|
||||
#define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
|
||||
#define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
|
||||
#define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
|
||||
#define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
|
||||
#define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
|
||||
#define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
|
||||
#define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
|
||||
#define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
|
||||
#define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
|
||||
#define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
|
||||
#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
|
||||
#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
|
||||
#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
|
||||
#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
|
||||
#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
|
||||
#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
|
||||
#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
|
||||
#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
|
||||
#define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
|
||||
s->priority1[irq][cpu] : \
|
||||
s->priority2[(irq) - GIC_INTERNAL])
|
||||
#define GIC_TARGET(irq) s->irq_target[irq]
|
||||
|
||||
typedef struct gic_irq_state {
|
||||
/* The enable bits are only banked for per-cpu interrupts. */
|
||||
unsigned enabled:NCPU;
|
||||
unsigned pending:NCPU;
|
||||
unsigned active:NCPU;
|
||||
unsigned level:NCPU;
|
||||
unsigned model:1; /* 0 = N:N, 1 = 1:N */
|
||||
unsigned trigger:1; /* nonzero = edge triggered. */
|
||||
} gic_irq_state;
|
||||
|
||||
typedef struct gic_state {
|
||||
SysBusDevice busdev;
|
||||
qemu_irq parent_irq[NCPU];
|
||||
int enabled;
|
||||
int cpu_enabled[NCPU];
|
||||
|
||||
gic_irq_state irq_state[GIC_MAXIRQ];
|
||||
int irq_target[GIC_MAXIRQ];
|
||||
int priority1[GIC_INTERNAL][NCPU];
|
||||
int priority2[GIC_MAXIRQ - GIC_INTERNAL];
|
||||
int last_active[GIC_MAXIRQ][NCPU];
|
||||
|
||||
int priority_mask[NCPU];
|
||||
int running_irq[NCPU];
|
||||
int running_priority[NCPU];
|
||||
int current_pending[NCPU];
|
||||
|
||||
uint32_t num_cpu;
|
||||
|
||||
MemoryRegion iomem; /* Distributor */
|
||||
/* This is just so we can have an opaque pointer which identifies
|
||||
* both this GIC and which CPU interface we should be accessing.
|
||||
*/
|
||||
struct gic_state *backref[NCPU];
|
||||
MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */
|
||||
uint32_t num_irq;
|
||||
uint32_t revision;
|
||||
} gic_state;
|
||||
|
||||
/* The special cases for the revision property: */
|
||||
#define REV_11MPCORE 0
|
||||
#define REV_NVIC 0xffffffff
|
||||
|
||||
void gic_set_pending_private(gic_state *s, int cpu, int irq);
|
||||
uint32_t gic_acknowledge_irq(gic_state *s, int cpu);
|
||||
void gic_complete_irq(gic_state *s, int cpu, int irq);
|
||||
void gic_update(gic_state *s);
|
||||
void gic_init_irqs_and_distributor(gic_state *s, int num_irq);
|
||||
|
||||
#define TYPE_ARM_GIC_COMMON "arm_gic_common"
|
||||
#define ARM_GIC_COMMON(obj) \
|
||||
OBJECT_CHECK(gic_state, (obj), TYPE_ARM_GIC_COMMON)
|
||||
#define ARM_GIC_COMMON_CLASS(klass) \
|
||||
OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON)
|
||||
#define ARM_GIC_COMMON_GET_CLASS(obj) \
|
||||
OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON)
|
||||
|
||||
typedef struct ARMGICCommonClass {
|
||||
SysBusDeviceClass parent_class;
|
||||
} ARMGICCommonClass;
|
||||
|
||||
#define TYPE_ARM_GIC "arm_gic"
|
||||
#define ARM_GIC(obj) \
|
||||
OBJECT_CHECK(gic_state, (obj), TYPE_ARM_GIC)
|
||||
#define ARM_GIC_CLASS(klass) \
|
||||
OBJECT_CLASS_CHECK(ARMGICClass, (klass), TYPE_ARM_GIC)
|
||||
#define ARM_GIC_GET_CLASS(obj) \
|
||||
OBJECT_GET_CLASS(ARMGICClass, (obj), TYPE_ARM_GIC)
|
||||
|
||||
typedef struct ARMGICClass {
|
||||
ARMGICCommonClass parent_class;
|
||||
int (*parent_init)(SysBusDevice *dev);
|
||||
} ARMGICClass;
|
||||
|
||||
#endif /* !QEMU_ARM_GIC_INTERNAL_H */
|
||||
@ -14,13 +14,7 @@
|
||||
#include "qemu-timer.h"
|
||||
#include "arm-misc.h"
|
||||
#include "exec-memory.h"
|
||||
|
||||
#define NVIC 1
|
||||
|
||||
static uint32_t nvic_readl(void *opaque, uint32_t offset);
|
||||
static void nvic_writel(void *opaque, uint32_t offset, uint32_t value);
|
||||
|
||||
#include "arm_gic.c"
|
||||
#include "arm_gic_internal.h"
|
||||
|
||||
typedef struct {
|
||||
gic_state gic;
|
||||
@ -36,6 +30,28 @@ typedef struct {
|
||||
uint32_t num_irq;
|
||||
} nvic_state;
|
||||
|
||||
#define TYPE_NVIC "armv7m_nvic"
|
||||
/**
|
||||
* NVICClass:
|
||||
* @parent_reset: the parent class' reset handler.
|
||||
*
|
||||
* A model of the v7M NVIC and System Controller
|
||||
*/
|
||||
typedef struct NVICClass {
|
||||
/*< private >*/
|
||||
ARMGICClass parent_class;
|
||||
/*< public >*/
|
||||
int (*parent_init)(SysBusDevice *dev);
|
||||
void (*parent_reset)(DeviceState *dev);
|
||||
} NVICClass;
|
||||
|
||||
#define NVIC_CLASS(klass) \
|
||||
OBJECT_CLASS_CHECK(NVICClass, (klass), TYPE_NVIC)
|
||||
#define NVIC_GET_CLASS(obj) \
|
||||
OBJECT_GET_CLASS(NVICClass, (obj), TYPE_NVIC)
|
||||
#define NVIC(obj) \
|
||||
OBJECT_CHECK(nvic_state, (obj), TYPE_NVIC)
|
||||
|
||||
static const uint8_t nvic_id[] = {
|
||||
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
|
||||
};
|
||||
@ -429,8 +445,9 @@ static const VMStateDescription vmstate_nvic = {
|
||||
|
||||
static void armv7m_nvic_reset(DeviceState *dev)
|
||||
{
|
||||
nvic_state *s = FROM_SYSBUSGIC(nvic_state, sysbus_from_qdev(dev));
|
||||
gic_reset(&s->gic.busdev.qdev);
|
||||
nvic_state *s = NVIC(dev);
|
||||
NVICClass *nc = NVIC_GET_CLASS(s);
|
||||
nc->parent_reset(dev);
|
||||
/* Common GIC reset resets to disabled; the NVIC doesn't have
|
||||
* per-CPU interfaces so mark our non-existent CPU interface
|
||||
* as enabled by default.
|
||||
@ -443,12 +460,15 @@ static void armv7m_nvic_reset(DeviceState *dev)
|
||||
|
||||
static int armv7m_nvic_init(SysBusDevice *dev)
|
||||
{
|
||||
nvic_state *s= FROM_SYSBUSGIC(nvic_state, dev);
|
||||
nvic_state *s = NVIC(dev);
|
||||
NVICClass *nc = NVIC_GET_CLASS(s);
|
||||
|
||||
/* The NVIC always has only one CPU */
|
||||
s->gic.num_cpu = 1;
|
||||
/* Tell the common code we're an NVIC */
|
||||
s->gic.revision = 0xffffffff;
|
||||
s->gic.num_irq = s->num_irq;
|
||||
nc->parent_init(dev);
|
||||
gic_init_irqs_and_distributor(&s->gic, s->num_irq);
|
||||
/* The NVIC and system controller register area looks like this:
|
||||
* 0..0xff : system control registers, including systick
|
||||
@ -489,9 +509,12 @@ static Property armv7m_nvic_properties[] = {
|
||||
|
||||
static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
NVICClass *nc = NVIC_CLASS(klass);
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
|
||||
|
||||
nc->parent_reset = dc->reset;
|
||||
nc->parent_init = sdc->init;
|
||||
sdc->init = armv7m_nvic_init;
|
||||
dc->vmsd = &vmstate_nvic;
|
||||
dc->reset = armv7m_nvic_reset;
|
||||
@ -499,10 +522,11 @@ static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
|
||||
}
|
||||
|
||||
static TypeInfo armv7m_nvic_info = {
|
||||
.name = "armv7m_nvic",
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.name = TYPE_NVIC,
|
||||
.parent = TYPE_ARM_GIC_COMMON,
|
||||
.instance_size = sizeof(nvic_state),
|
||||
.class_init = armv7m_nvic_class_init,
|
||||
.class_size = sizeof(NVICClass),
|
||||
};
|
||||
|
||||
static void armv7m_nvic_register_types(void)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user