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target/microblaze: Convert dec_add to decodetree
Adds infrastrucure for translation of instructions, which could not be added before their first use. Cache a temporary which represents r0 as the immediate 0 value, or a sink. Move the special case of opcode_0_illegal from old_decode() into decodetree as well, lest this get interpreted as add. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
44d1432ba2
commit
2080017965
@ -16,3 +16,27 @@
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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&typea rd ra rb
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&typeb rd ra imm
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# Include any IMM prefix in the value reported.
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%extimm 0:s16 !function=typeb_imm
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@typea ...... rd:5 ra:5 rb:5 ... .... .... &typea
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@typeb ...... rd:5 ra:5 ................ &typeb imm=%extimm
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###
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{
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zero 000000 00000 00000 00000 000 0000 0000
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add 000000 ..... ..... ..... 000 0000 0000 @typea
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}
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addc 000010 ..... ..... ..... 000 0000 0000 @typea
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addk 000100 ..... ..... ..... 000 0000 0000 @typea
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addkc 000110 ..... ..... ..... 000 0000 0000 @typea
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addi 001000 ..... ..... ................ @typeb
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addic 001010 ..... ..... ................ @typeb
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addik 001100 ..... ..... ................ @typeb
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addikc 001110 ..... ..... ................ @typeb
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@ -58,6 +58,9 @@ typedef struct DisasContext {
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DisasContextBase base;
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MicroBlazeCPU *cpu;
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TCGv_i32 r0;
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bool r0_set;
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/* Decoder. */
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int type_b;
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uint32_t ir;
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@ -81,6 +84,14 @@ typedef struct DisasContext {
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int abort_at_next_insn;
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} DisasContext;
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static int typeb_imm(DisasContext *dc, int x)
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{
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if (dc->tb_flags & IMM_FLAG) {
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return deposit32(dc->ext_imm, 0, 16, x);
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}
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return x;
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}
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/* Include the auto-generated decoder. */
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#include "decode-insns.c.inc"
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@ -176,11 +187,7 @@ static bool trap_userspace(DisasContext *dc, bool cond)
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static int32_t dec_alu_typeb_imm(DisasContext *dc)
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{
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tcg_debug_assert(dc->type_b);
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if (dc->tb_flags & IMM_FLAG) {
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return dc->ext_imm | dc->imm;
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} else {
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return (int16_t)dc->imm;
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}
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return typeb_imm(dc, (int16_t)dc->imm);
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}
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static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc)
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@ -192,44 +199,146 @@ static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc)
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return &cpu_R[dc->rb];
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}
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static void dec_add(DisasContext *dc)
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static TCGv_i32 reg_for_read(DisasContext *dc, int reg)
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{
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unsigned int k, c;
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TCGv_i32 cf;
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k = dc->opcode & 4;
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c = dc->opcode & 2;
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/* Take care of the easy cases first. */
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if (k) {
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/* k - keep carry, no need to update MSR. */
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/* If rd == r0, it's a nop. */
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if (dc->rd) {
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tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
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if (c) {
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/* c - Add carry into the result. */
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tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c);
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}
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if (likely(reg != 0)) {
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return cpu_R[reg];
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}
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if (!dc->r0_set) {
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if (dc->r0 == NULL) {
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dc->r0 = tcg_temp_new_i32();
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}
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return;
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tcg_gen_movi_i32(dc->r0, 0);
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dc->r0_set = true;
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}
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return dc->r0;
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}
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static TCGv_i32 reg_for_write(DisasContext *dc, int reg)
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{
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if (likely(reg != 0)) {
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return cpu_R[reg];
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}
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if (dc->r0 == NULL) {
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dc->r0 = tcg_temp_new_i32();
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}
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return dc->r0;
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}
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static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects,
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void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32))
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{
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TCGv_i32 rd, ra, rb;
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if (arg->rd == 0 && !side_effects) {
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return true;
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}
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/* From now on, we can assume k is zero. So we need to update MSR. */
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/* Extract carry. */
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cf = tcg_temp_new_i32();
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if (c) {
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tcg_gen_mov_i32(cf, cpu_msr_c);
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} else {
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tcg_gen_movi_i32(cf, 0);
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rd = reg_for_write(dc, arg->rd);
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ra = reg_for_read(dc, arg->ra);
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rb = reg_for_read(dc, arg->rb);
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fn(rd, ra, rb);
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return true;
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}
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static bool do_typeb_imm(DisasContext *dc, arg_typeb *arg, bool side_effects,
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void (*fni)(TCGv_i32, TCGv_i32, int32_t))
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{
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TCGv_i32 rd, ra;
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if (arg->rd == 0 && !side_effects) {
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return true;
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}
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gen_helper_carry(cpu_msr_c, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
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if (dc->rd) {
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tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
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tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf);
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rd = reg_for_write(dc, arg->rd);
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ra = reg_for_read(dc, arg->ra);
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fni(rd, ra, arg->imm);
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return true;
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}
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static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects,
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void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32))
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{
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TCGv_i32 rd, ra, imm;
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if (arg->rd == 0 && !side_effects) {
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return true;
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}
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tcg_temp_free_i32(cf);
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rd = reg_for_write(dc, arg->rd);
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ra = reg_for_read(dc, arg->ra);
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imm = tcg_const_i32(arg->imm);
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fn(rd, ra, imm);
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tcg_temp_free_i32(imm);
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return true;
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}
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#define DO_TYPEA(NAME, SE, FN) \
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static bool trans_##NAME(DisasContext *dc, arg_typea *a) \
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{ return do_typea(dc, a, SE, FN); }
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#define DO_TYPEBI(NAME, SE, FNI) \
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static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \
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{ return do_typeb_imm(dc, a, SE, FNI); }
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#define DO_TYPEBV(NAME, SE, FN) \
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static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \
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{ return do_typeb_val(dc, a, SE, FN); }
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/* No input carry, but output carry. */
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static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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{
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TCGv_i32 zero = tcg_const_i32(0);
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tcg_gen_add2_i32(out, cpu_msr_c, ina, zero, inb, zero);
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tcg_temp_free_i32(zero);
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}
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/* Input and output carry. */
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static void gen_addc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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{
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TCGv_i32 zero = tcg_const_i32(0);
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_add2_i32(tmp, cpu_msr_c, ina, zero, cpu_msr_c, zero);
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tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero);
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(zero);
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}
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/* Input carry, but no output carry. */
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static void gen_addkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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{
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tcg_gen_add_i32(out, ina, inb);
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tcg_gen_add_i32(out, out, cpu_msr_c);
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}
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DO_TYPEA(add, true, gen_add)
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DO_TYPEA(addc, true, gen_addc)
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DO_TYPEA(addk, false, tcg_gen_add_i32)
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DO_TYPEA(addkc, true, gen_addkc)
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DO_TYPEBV(addi, true, gen_add)
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DO_TYPEBV(addic, true, gen_addc)
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DO_TYPEBI(addik, false, tcg_gen_addi_i32)
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DO_TYPEBV(addikc, true, gen_addkc)
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static bool trans_zero(DisasContext *dc, arg_zero *arg)
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{
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/* If opcode_0_illegal, trap. */
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if (dc->cpu->cfg.opcode_0_illegal) {
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trap_illegal(dc, true);
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return true;
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}
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/*
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* Otherwise, this is "add r0, r0, r0".
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* Continue to trans_add so that MSR[C] gets cleared.
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*/
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return false;
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}
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static void dec_sub(DisasContext *dc)
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@ -1488,7 +1597,6 @@ static struct decoder_info {
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};
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void (*dec)(DisasContext *dc);
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} decinfo[] = {
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{DEC_ADD, dec_add},
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{DEC_SUB, dec_sub},
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{DEC_AND, dec_and},
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{DEC_XOR, dec_xor},
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@ -1515,12 +1623,6 @@ static void old_decode(DisasContext *dc, uint32_t ir)
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dc->ir = ir;
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if (ir == 0) {
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trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal);
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/* Don't decode nop/zero instructions any further. */
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return;
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}
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/* bit 2 seems to indicate insn type. */
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dc->type_b = ir & (1 << 29);
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@ -1552,6 +1654,8 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
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dc->cpustate_changed = 0;
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dc->abort_at_next_insn = 0;
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dc->ext_imm = dc->base.tb->cs_base;
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dc->r0 = NULL;
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dc->r0_set = false;
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bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
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dc->base.max_insns = MIN(dc->base.max_insns, bound);
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@ -1600,6 +1704,13 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
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if (!decode(dc, ir)) {
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old_decode(dc, ir);
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}
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if (dc->r0) {
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tcg_temp_free_i32(dc->r0);
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dc->r0 = NULL;
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dc->r0_set = false;
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}
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if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) {
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dc->tb_flags &= ~IMM_FLAG;
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tcg_gen_discard_i32(cpu_imm);
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