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armv7-m: Return DeviceState* from armv7m_init()
Change armv7m_init to return the DeviceState* for the NVIC. This allows access to all GPIO blocks, not just the IRQ inputs. Move qdev_get_gpio_in() calls out of armv7m_init() into board code for stellaris and stm32f205 boards. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Michael Davidsaver
Peter Maydell
parent
c3a9a689c6
commit
20c59c3892
@ -166,17 +166,15 @@ static void armv7m_reset(void *opaque)
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mem_size is in bytes.
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Returns the NVIC array. */
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qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
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DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
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const char *kernel_filename, const char *cpu_model)
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{
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ARMCPU *cpu;
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CPUARMState *env;
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DeviceState *nvic;
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qemu_irq *pic = g_new(qemu_irq, num_irq);
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int image_size;
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uint64_t entry;
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uint64_t lowaddr;
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int i;
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int big_endian;
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MemoryRegion *hack = g_new(MemoryRegion, 1);
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@ -198,9 +196,6 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
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qdev_init_nofail(nvic);
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sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
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qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
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for (i = 0; i < num_irq; i++) {
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pic[i] = qdev_get_gpio_in(nvic, i);
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}
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#ifdef TARGET_WORDS_BIGENDIAN
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big_endian = 1;
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@ -234,7 +229,7 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
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memory_region_add_subregion(system_memory, 0xfffff000, hack);
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qemu_register_reset(armv7m_reset, cpu);
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return pic;
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return nvic;
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}
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static Property bitband_properties[] = {
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@ -1210,8 +1210,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
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0x40024000, 0x40025000, 0x40026000};
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static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
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qemu_irq *pic;
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DeviceState *gpio_dev[7];
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DeviceState *gpio_dev[7], *nvic;
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qemu_irq gpio_in[7][8];
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qemu_irq gpio_out[7][8];
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qemu_irq adc;
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@ -1241,12 +1240,16 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
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vmstate_register_ram_global(sram);
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memory_region_add_subregion(system_memory, 0x20000000, sram);
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pic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,
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nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,
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kernel_filename, cpu_model);
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if (board->dc1 & (1 << 16)) {
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dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
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pic[14], pic[15], pic[16], pic[17], NULL);
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qdev_get_gpio_in(nvic, 14),
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qdev_get_gpio_in(nvic, 15),
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qdev_get_gpio_in(nvic, 16),
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qdev_get_gpio_in(nvic, 17),
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NULL);
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adc = qdev_get_gpio_in(dev, 0);
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} else {
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adc = NULL;
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@ -1255,19 +1258,21 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
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if (board->dc2 & (0x10000 << i)) {
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dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
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0x40030000 + i * 0x1000,
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pic[timer_irq[i]]);
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qdev_get_gpio_in(nvic, timer_irq[i]));
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/* TODO: This is incorrect, but we get away with it because
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the ADC output is only ever pulsed. */
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qdev_connect_gpio_out(dev, 0, adc);
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}
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}
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stellaris_sys_init(0x400fe000, pic[28], board, nd_table[0].macaddr.a);
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stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
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board, nd_table[0].macaddr.a);
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for (i = 0; i < 7; i++) {
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if (board->dc4 & (1 << i)) {
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gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
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pic[gpio_irq[i]]);
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qdev_get_gpio_in(nvic,
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gpio_irq[i]));
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for (j = 0; j < 8; j++) {
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gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
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gpio_out[i][j] = NULL;
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@ -1276,7 +1281,8 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
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}
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if (board->dc2 & (1 << 12)) {
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dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, pic[8]);
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dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
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qdev_get_gpio_in(nvic, 8));
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i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
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if (board->peripherals & BP_OLED_I2C) {
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i2c_create_slave(i2c, "ssd0303", 0x3d);
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@ -1286,11 +1292,12 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
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for (i = 0; i < 4; i++) {
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if (board->dc2 & (1 << i)) {
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sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000,
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pic[uart_irq[i]]);
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qdev_get_gpio_in(nvic, uart_irq[i]));
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}
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}
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if (board->dc2 & (1 << 4)) {
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dev = sysbus_create_simple("pl022", 0x40008000, pic[7]);
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dev = sysbus_create_simple("pl022", 0x40008000,
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qdev_get_gpio_in(nvic, 7));
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if (board->peripherals & BP_OLED_SSI) {
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void *bus;
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DeviceState *sddev;
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@ -1326,7 +1333,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
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qdev_set_nic_properties(enet, &nd_table[0]);
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qdev_init_nofail(enet);
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sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
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sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, pic[42]);
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sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
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}
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if (board->peripherals & BP_GAMEPAD) {
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qemu_irq gpad_irq[5];
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@ -59,9 +59,8 @@ static void stm32f205_soc_initfn(Object *obj)
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static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
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{
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STM32F205State *s = STM32F205_SOC(dev_soc);
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DeviceState *syscfgdev, *usartdev, *timerdev;
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DeviceState *syscfgdev, *usartdev, *timerdev, *nvic;
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SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;
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qemu_irq *pic;
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Error *err = NULL;
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int i;
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@ -88,7 +87,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
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vmstate_register_ram_global(sram);
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memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
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pic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
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nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
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s->kernel_filename, s->cpu_model);
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/* System configuration controller */
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@ -100,7 +99,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
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}
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syscfgbusdev = SYS_BUS_DEVICE(syscfgdev);
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sysbus_mmio_map(syscfgbusdev, 0, 0x40013800);
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sysbus_connect_irq(syscfgbusdev, 0, pic[71]);
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sysbus_connect_irq(syscfgbusdev, 0, qdev_get_gpio_in(nvic, 71));
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/* Attach UART (uses USART registers) and USART controllers */
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for (i = 0; i < STM_NUM_USARTS; i++) {
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@ -112,7 +111,8 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
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}
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usartbusdev = SYS_BUS_DEVICE(usartdev);
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sysbus_mmio_map(usartbusdev, 0, usart_addr[i]);
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sysbus_connect_irq(usartbusdev, 0, pic[usart_irq[i]]);
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sysbus_connect_irq(usartbusdev, 0,
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qdev_get_gpio_in(nvic, usart_irq[i]));
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}
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/* Timer 2 to 5 */
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@ -126,7 +126,8 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
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}
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timerbusdev = SYS_BUS_DEVICE(timerdev);
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sysbus_mmio_map(timerbusdev, 0, timer_addr[i]);
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sysbus_connect_irq(timerbusdev, 0, pic[timer_irq[i]]);
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sysbus_connect_irq(timerbusdev, 0,
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qdev_get_gpio_in(nvic, timer_irq[i]));
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}
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}
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@ -17,7 +17,7 @@
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#include "cpu.h"
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/* armv7m.c */
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qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
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DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
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const char *kernel_filename, const char *cpu_model);
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/*
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