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ppc/xics: preserve P and Q bits for KVM IRQs
Kernel commit 17d48610ae0f ("KVM: PPC: Book 3S: XICS: Implement ICS P/Q states") added new bits to the state used by KVM IRQs. Currently, QEMU does not preserve these bits, so migrating (or otherwise saving and restoring) the guest state causes the P and Q bits to be cleared. Clearing the P bit has no effect, because the kernel will set it based on other data, but the loss of a set Q bit will cause a lost interrupt. This patch preserves the P and Q bits, correcting the problem. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -229,6 +229,12 @@ static void ics_get_kvm_state(ICSState *ics)
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| XICS_STATUS_REJECTED;
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}
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}
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if (state & KVM_XICS_PRESENTED) {
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irq->status |= XICS_STATUS_PRESENTED;
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}
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if (state & KVM_XICS_QUEUED) {
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irq->status |= XICS_STATUS_QUEUED;
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}
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}
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}
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@ -266,6 +272,12 @@ static int ics_set_kvm_state(ICSState *ics, int version_id)
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state |= KVM_XICS_PENDING;
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}
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}
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if (irq->status & XICS_STATUS_PRESENTED) {
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state |= KVM_XICS_PRESENTED;
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}
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if (irq->status & XICS_STATUS_QUEUED) {
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state |= KVM_XICS_QUEUED;
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}
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ret = ioctl(kernel_xics_fd, KVM_SET_DEVICE_ATTR, &attr);
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if (ret != 0) {
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@ -144,6 +144,8 @@ struct ICSIRQState {
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#define XICS_STATUS_SENT 0x2
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#define XICS_STATUS_REJECTED 0x4
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#define XICS_STATUS_MASKED_PENDING 0x8
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#define XICS_STATUS_PRESENTED 0x10
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#define XICS_STATUS_QUEUED 0x20
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uint8_t status;
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/* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
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#define XICS_FLAGS_IRQ_LSI 0x1
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