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tcg/i386: Implement avx512 immediate sari shift

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AVX512 has VPSRAQ with immediate operand, in the same form as
with AVX, but requires EVEX encoding and W1.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-12-17 20:16:43 -08:00
parent 47b331b2a8
commit 264e418230
1 changed files with 21 additions and 9 deletions
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30
tcg/i386/tcg-target.c.inc
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@ -2986,17 +2986,22 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_shli_vec:
insn = shift_imm_insn[vece];
sub = 6;
goto gen_shift;
case INDEX_op_shri_vec:
insn = shift_imm_insn[vece];
sub = 2;
goto gen_shift;
case INDEX_op_sari_vec:
tcg_debug_assert(vece != MO_64);
if (vece == MO_64) {
insn = OPC_PSHIFTD_Ib | P_VEXW | P_EVEX;
} else {
insn = shift_imm_insn[vece];
}
sub = 4;
gen_shift:
tcg_debug_assert(vece != MO_8);
insn = shift_imm_insn[vece];
if (type == TCG_TYPE_V256) {
insn |= P_VEXL;
}
@ -3316,16 +3321,23 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
return vece == MO_8 ? -1 : 1;
case INDEX_op_sari_vec:
/* We must expand the operation for MO_8. */
if (vece == MO_8) {
switch (vece) {
case MO_8:
return -1;
}
/* We can emulate this for MO_64, but it does not pay off
unless we're producing at least 4 values. */
if (vece == MO_64) {
case MO_16:
case MO_32:
return 1;
case MO_64:
if (have_avx512vl) {
return 1;
}
/*
* We can emulate this for MO_64, but it does not pay off
* unless we're producing at least 4 values.
*/
return type >= TCG_TYPE_V256 ? -1 : 0;
}
return 1;
return 0;
case INDEX_op_shls_vec:
case INDEX_op_shrs_vec: