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ppc/ppc405: QOM'ify GPT
The GPT controller is currently modeled as a SysBus device with a unique memory region, a couple of IRQs and a timer. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> [balaton: ppc4xx_dcr_register changes, add finalize method] Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <8950ab26e78173f94ba65bc61bcfd0631de1fe61.1660746880.git.balaton@eik.bme.hu> [danielhb: check if timer != NULL in ppc405_gpt_finalize()] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Cédric Le Goater
Daniel Henrique Barboza
parent
4a7d2b7e5c
commit
269fbb5b8a
@ -63,6 +63,27 @@ struct ppc4xx_bd_info_t {
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uint32_t bi_iic_fast[2];
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};
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/* General purpose timers */
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#define TYPE_PPC405_GPT "ppc405-gpt"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
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struct Ppc405GptState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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int64_t tb_offset;
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uint32_t tb_freq;
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QEMUTimer *timer;
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qemu_irq irqs[5];
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uint32_t oe;
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uint32_t ol;
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uint32_t im;
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uint32_t is;
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uint32_t ie;
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uint32_t comp[5];
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uint32_t mask[5];
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};
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#define TYPE_PPC405_CPC "ppc405-cpc"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
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@ -114,6 +135,7 @@ struct Ppc405SoCState {
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PowerPCCPU cpu;
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DeviceState *uic;
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Ppc405CpcState cpc;
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Ppc405GptState gpt;
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};
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/* PowerPC 405 core */
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@ -926,34 +926,18 @@ static void ppc405_ocm_init(CPUPPCState *env)
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/*****************************************************************************/
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/* General purpose timers */
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typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
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struct ppc4xx_gpt_t {
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MemoryRegion iomem;
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int64_t tb_offset;
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uint32_t tb_freq;
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QEMUTimer *timer;
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qemu_irq irqs[5];
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uint32_t oe;
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uint32_t ol;
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uint32_t im;
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uint32_t is;
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uint32_t ie;
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uint32_t comp[5];
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uint32_t mask[5];
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};
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static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
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static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n)
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{
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/* XXX: TODO */
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return 0;
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}
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static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
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static void ppc4xx_gpt_set_output(Ppc405GptState *gpt, int n, int level)
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{
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/* XXX: TODO */
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}
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static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
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static void ppc4xx_gpt_set_outputs(Ppc405GptState *gpt)
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{
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uint32_t mask;
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int i;
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@ -974,7 +958,7 @@ static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
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}
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}
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static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
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static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt)
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{
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uint32_t mask;
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int i;
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@ -989,14 +973,14 @@ static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
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}
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}
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static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
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static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt)
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{
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/* XXX: TODO */
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}
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static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
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{
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ppc4xx_gpt_t *gpt = opaque;
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Ppc405GptState *gpt = opaque;
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uint32_t ret;
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int idx;
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@ -1050,7 +1034,7 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
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static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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ppc4xx_gpt_t *gpt = opaque;
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Ppc405GptState *gpt = opaque;
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int idx;
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trace_ppc4xx_gpt_write(addr, size, value);
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@ -1114,22 +1098,20 @@ static const MemoryRegionOps gpt_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void ppc4xx_gpt_cb (void *opaque)
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static void ppc4xx_gpt_cb(void *opaque)
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{
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ppc4xx_gpt_t *gpt;
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Ppc405GptState *gpt = opaque;
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gpt = opaque;
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ppc4xx_gpt_set_irqs(gpt);
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ppc4xx_gpt_set_outputs(gpt);
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ppc4xx_gpt_compute_timer(gpt);
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}
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static void ppc4xx_gpt_reset (void *opaque)
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static void ppc405_gpt_reset(DeviceState *dev)
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{
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ppc4xx_gpt_t *gpt;
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Ppc405GptState *gpt = PPC405_GPT(dev);
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int i;
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gpt = opaque;
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timer_del(gpt->timer);
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gpt->oe = 0x00000000;
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gpt->ol = 0x00000000;
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@ -1142,21 +1124,37 @@ static void ppc4xx_gpt_reset (void *opaque)
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}
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}
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static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
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static void ppc405_gpt_realize(DeviceState *dev, Error **errp)
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{
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ppc4xx_gpt_t *gpt;
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Ppc405GptState *s = PPC405_GPT(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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int i;
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trace_ppc4xx_gpt_init(base);
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s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, s);
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memory_region_init_io(&s->iomem, OBJECT(s), &gpt_ops, s, "gpt", 0xd4);
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sysbus_init_mmio(sbd, &s->iomem);
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gpt = g_new0(ppc4xx_gpt_t, 1);
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for (i = 0; i < 5; i++) {
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gpt->irqs[i] = irqs[i];
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for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
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sysbus_init_irq(sbd, &s->irqs[i]);
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}
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gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
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memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
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memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
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qemu_register_reset(ppc4xx_gpt_reset, gpt);
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}
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static void ppc405_gpt_finalize(Object *obj)
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{
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/* timer will be NULL if the GPT wasn't realized */
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if (PPC405_GPT(obj)->timer) {
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timer_del(PPC405_GPT(obj)->timer);
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}
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}
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static void ppc405_gpt_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = ppc405_gpt_realize;
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dc->reset = ppc405_gpt_reset;
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/* Reason: only works as function of a ppc4xx SoC */
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dc->user_creatable = false;
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}
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/*****************************************************************************/
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@ -1420,6 +1418,8 @@ static void ppc405_soc_instance_init(Object *obj)
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object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
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object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
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object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
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}
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static void ppc405_reset(void *opaque)
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@ -1430,8 +1430,10 @@ static void ppc405_reset(void *opaque)
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static void ppc405_soc_realize(DeviceState *dev, Error **errp)
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{
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Ppc405SoCState *s = PPC405_SOC(dev);
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qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
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qemu_irq dma_irqs[4], mal_irqs[4];
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CPUPPCState *env;
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SysBusDevice *sbd;
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int i;
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/* init CPUs */
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if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
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@ -1517,12 +1519,14 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
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ppc405_ocm_init(env);
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/* GPT */
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gpt_irqs[0] = qdev_get_gpio_in(s->uic, 19);
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gpt_irqs[1] = qdev_get_gpio_in(s->uic, 20);
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gpt_irqs[2] = qdev_get_gpio_in(s->uic, 21);
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gpt_irqs[3] = qdev_get_gpio_in(s->uic, 22);
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gpt_irqs[4] = qdev_get_gpio_in(s->uic, 23);
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ppc4xx_gpt_init(0xef600000, gpt_irqs);
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sbd = SYS_BUS_DEVICE(&s->gpt);
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if (!sysbus_realize(sbd, errp)) {
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return;
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}
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sysbus_mmio_map(sbd, 0, 0xef600000);
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for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
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sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 19 + i));
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}
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/* MAL */
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mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
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@ -1555,6 +1559,12 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
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static const TypeInfo ppc405_types[] = {
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{
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.name = TYPE_PPC405_GPT,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Ppc405GptState),
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.instance_finalize = ppc405_gpt_finalize,
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.class_init = ppc405_gpt_class_init,
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}, {
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.name = TYPE_PPC405_CPC,
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.parent = TYPE_PPC4xx_DCR_DEVICE,
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.instance_size = sizeof(Ppc405CpcState),
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@ -173,7 +173,6 @@ ocm_unmap(const char* prefix, uint32_t isarc) "OCM unmap %s 0x%08" PRIx32
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ppc4xx_gpt_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
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ppc4xx_gpt_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64
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ppc4xx_gpt_init(uint64_t addr) "offet 0x%" PRIx64
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ppc405ep_clocks_compute(const char *param, uint32_t param2, uint32_t val) "%s 0x%1" PRIx32 " %d"
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ppc405ep_clocks_setup(const char *trace) "%s"
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