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target/ppc: Move VABSDU[BHW] to decodetree and use gvec
Moved VABSDUB, VABSDUH and VABSDUW to decodetree and use gvec to translate them. vabsdub: rept loop master patch 8 12500 0,03601600 0,00688500 (-80.9%) 25 4000 0,03651000 0,00532100 (-85.4%) 100 1000 0,03666900 0,00595300 (-83.8%) 500 200 0,04305800 0,01244600 (-71.1%) 2500 40 0,06893300 0,04273700 (-38.0%) 8000 12 0,14633200 0,12660300 (-13.5%) vabsduh: rept loop master patch 8 12500 0,02172400 0,00687500 (-68.4%) 25 4000 0,02154100 0,00531500 (-75.3%) 100 1000 0,02235400 0,00596300 (-73.3%) 500 200 0,02827500 0,01245100 (-56.0%) 2500 40 0,05638400 0,04285500 (-24.0%) 8000 12 0,13166000 0,12641400 (-4.0%) vabsduw: rept loop master patch 8 12500 0,01646400 0,00688300 (-58.2%) 25 4000 0,01454500 0,00475500 (-67.3%) 100 1000 0,01545800 0,00511800 (-66.9%) 500 200 0,02168200 0,01114300 (-48.6%) 2500 40 0,04571300 0,04138800 (-9.5%) 8000 12 0,12209500 0,12178500 (-0.3%) Same as VADDCUW and VSUBCUW, overall performance gain but it uses more TCGop (4 before the patch, 6 after). Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221019125040.48028-8-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Lucas Mateus Castro (alqotel)
Daniel Henrique Barboza
parent
c85929b2dd
commit
26c964f851
@ -146,9 +146,9 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64)
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DEF_HELPER_FLAGS_4(VAVGUB, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
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DEF_HELPER_FLAGS_4(VAVGUH, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
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DEF_HELPER_FLAGS_4(VAVGUW, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
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DEF_HELPER_FLAGS_3(vabsdub, TCG_CALL_NO_RWG, void, avr, avr, avr)
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DEF_HELPER_FLAGS_3(vabsduh, TCG_CALL_NO_RWG, void, avr, avr, avr)
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DEF_HELPER_FLAGS_3(vabsduw, TCG_CALL_NO_RWG, void, avr, avr, avr)
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DEF_HELPER_FLAGS_4(VABSDUB, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
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DEF_HELPER_FLAGS_4(VABSDUH, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
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DEF_HELPER_FLAGS_4(VABSDUW, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
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DEF_HELPER_FLAGS_4(VAVGSB, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
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DEF_HELPER_FLAGS_4(VAVGSH, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
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DEF_HELPER_FLAGS_4(VAVGSW, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
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@ -528,6 +528,12 @@ VAVGUB 000100 ..... ..... ..... 10000000010 @VX
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VAVGUH 000100 ..... ..... ..... 10001000010 @VX
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VAVGUW 000100 ..... ..... ..... 10010000010 @VX
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## Vector Integer Absolute Difference Instructions
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VABSDUB 000100 ..... ..... ..... 10000000011 @VX
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VABSDUH 000100 ..... ..... ..... 10001000011 @VX
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VABSDUW 000100 ..... ..... ..... 10010000011 @VX
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## Vector Bit Manipulation Instruction
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VGNB 000100 ..... -- ... ..... 10011001100 @VX_n
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@ -589,8 +589,8 @@ VAVG(VAVGSW, s32, int64_t)
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VAVG(VAVGUW, u32, uint64_t)
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#undef VAVG
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#define VABSDU_DO(name, element) \
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void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
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#define VABSDU(name, element) \
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void helper_##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t v)\
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{ \
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int i; \
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\
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@ -606,12 +606,9 @@ void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
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* name - instruction mnemonic suffix (b: byte, h: halfword, w: word)
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* element - element type to access from vector
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*/
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#define VABSDU(type, element) \
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VABSDU_DO(absdu##type, element)
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VABSDU(b, u8)
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VABSDU(h, u16)
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VABSDU(w, u32)
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#undef VABSDU_DO
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VABSDU(VABSDUB, u8)
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VABSDU(VABSDUH, u16)
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VABSDU(VABSDUW, u32)
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#undef VABSDU
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#define VCF(suffix, cvt, element) \
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@ -431,9 +431,6 @@ GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);
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GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);
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GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);
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GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);
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GEN_VXFORM(vabsdub, 1, 16);
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GEN_VXFORM(vabsduh, 1, 17);
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GEN_VXFORM(vabsduw, 1, 18);
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GEN_VXFORM(vmrghb, 6, 0);
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GEN_VXFORM(vmrghh, 6, 1);
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GEN_VXFORM(vmrghw, 6, 2);
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@ -3455,6 +3452,52 @@ TRANS_FLAGS(ALTIVEC, VAVGUB, do_vx_vavg, 0, MO_8)
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TRANS_FLAGS(ALTIVEC, VAVGUH, do_vx_vavg, 0, MO_16)
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TRANS_FLAGS(ALTIVEC, VAVGUW, do_vx_vavg, 0, MO_32)
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static void gen_vabsdu(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
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{
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tcg_gen_umax_vec(vece, t, a, b);
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tcg_gen_umin_vec(vece, a, a, b);
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tcg_gen_sub_vec(vece, t, t, a);
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}
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static bool do_vabsdu(DisasContext *ctx, arg_VX *a, const int vece)
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{
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static const TCGOpcode vecop_list[] = {
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INDEX_op_umax_vec, INDEX_op_umin_vec, INDEX_op_sub_vec, 0
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};
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static const GVecGen3 op[] = {
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{
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.fniv = gen_vabsdu,
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.fno = gen_helper_VABSDUB,
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.opt_opc = vecop_list,
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.vece = MO_8
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},
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{
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.fniv = gen_vabsdu,
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.fno = gen_helper_VABSDUH,
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.opt_opc = vecop_list,
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.vece = MO_16
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},
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{
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.fniv = gen_vabsdu,
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.fno = gen_helper_VABSDUW,
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.opt_opc = vecop_list,
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.vece = MO_32
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},
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};
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REQUIRE_VECTOR(ctx);
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tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
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avr_full_offset(a->vrb), 16, 16, &op[vece]);
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return true;
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}
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TRANS_FLAGS2(ISA300, VABSDUB, do_vabsdu, MO_8)
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TRANS_FLAGS2(ISA300, VABSDUH, do_vabsdu, MO_16)
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TRANS_FLAGS2(ISA300, VABSDUW, do_vabsdu, MO_32)
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static bool do_vdiv_vmod(DisasContext *ctx, arg_VX *a, const int vece,
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void (*func_32)(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b),
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void (*func_64)(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b))
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@ -83,9 +83,6 @@ GEN_VXFORM(vminsb, 1, 12),
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GEN_VXFORM(vminsh, 1, 13),
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GEN_VXFORM(vminsw, 1, 14),
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GEN_VXFORM_207(vminsd, 1, 15),
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GEN_VXFORM(vabsdub, 1, 16),
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GEN_VXFORM(vabsduh, 1, 17),
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GEN_VXFORM(vabsduw, 1, 18),
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GEN_VXFORM(vmrghb, 6, 0),
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GEN_VXFORM(vmrghh, 6, 1),
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GEN_VXFORM(vmrghw, 6, 2),
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