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PPC: E500: Inject SPE exception on invalid SPE access

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When accessing an SPE instruction despite it being not available,
throw an SPE exception instead of an APU exception. That way the
guest knows what's going on and actually uses SPE.

Reported-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Alexander Graf 2011-08-23 06:55:43 +02:00 committed by Edgar E. Iglesias
parent 542df9bfb7
commit 27a69bb088
1 changed files with 39 additions and 39 deletions
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78
target-ppc/translate.c
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@ -6622,7 +6622,7 @@ static inline void gen_evmra(DisasContext *ctx)
{ {
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
@ -6693,7 +6693,7 @@ static inline void gen_speundef(DisasContext *ctx)
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@ -6704,7 +6704,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@ -6729,7 +6729,7 @@ GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
TCGv_i32 t0 = tcg_temp_local_new_i32(); \ TCGv_i32 t0 = tcg_temp_local_new_i32(); \
@ -6750,7 +6750,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@ -6770,7 +6770,7 @@ GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
TCGv_i32 t0 = tcg_temp_local_new_i32(); \ TCGv_i32 t0 = tcg_temp_local_new_i32(); \
@ -6791,7 +6791,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
@ -6829,7 +6829,7 @@ GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
TCGv_i32 t0 = tcg_temp_local_new_i32(); \ TCGv_i32 t0 = tcg_temp_local_new_i32(); \
@ -6855,7 +6855,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@ -6933,7 +6933,7 @@ GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
static inline void gen_evmergehi(DisasContext *ctx) static inline void gen_evmergehi(DisasContext *ctx)
{ {
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
@ -6962,7 +6962,7 @@ GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
TCGv_i32 t0 = tcg_temp_local_new_i32(); \ TCGv_i32 t0 = tcg_temp_local_new_i32(); \
@ -6983,7 +6983,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
@ -7001,7 +7001,7 @@ GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
int l1 = gen_new_label(); \ int l1 = gen_new_label(); \
@ -7041,7 +7041,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
int l1 = gen_new_label(); \ int l1 = gen_new_label(); \
@ -7084,7 +7084,7 @@ static inline void gen_brinc(DisasContext *ctx)
static inline void gen_evmergelo(DisasContext *ctx) static inline void gen_evmergelo(DisasContext *ctx)
{ {
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
@ -7103,7 +7103,7 @@ static inline void gen_evmergelo(DisasContext *ctx)
static inline void gen_evmergehilo(DisasContext *ctx) static inline void gen_evmergehilo(DisasContext *ctx)
{ {
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
@ -7122,7 +7122,7 @@ static inline void gen_evmergehilo(DisasContext *ctx)
static inline void gen_evmergelohi(DisasContext *ctx) static inline void gen_evmergelohi(DisasContext *ctx)
{ {
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
@ -7245,7 +7245,7 @@ static inline void gen_evmwumi(DisasContext *ctx)
TCGv_i64 t0, t1; TCGv_i64 t0, t1;
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
@ -7274,7 +7274,7 @@ static inline void gen_evmwumia(DisasContext *ctx)
TCGv_i64 tmp; TCGv_i64 tmp;
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
@ -7294,7 +7294,7 @@ static inline void gen_evmwumiaa(DisasContext *ctx)
TCGv_i64 tmp; TCGv_i64 tmp;
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
@ -7327,7 +7327,7 @@ static inline void gen_evmwsmi(DisasContext *ctx)
TCGv_i64 t0, t1; TCGv_i64 t0, t1;
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
@ -7746,7 +7746,7 @@ static void glue(gen_, name)(DisasContext *ctx)
{ \ { \
TCGv t0; \ TCGv t0; \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
gen_set_access_type(ctx, ACCESS_INT); \ gen_set_access_type(ctx, ACCESS_INT); \
@ -7904,7 +7904,7 @@ static inline void gen_##name(DisasContext *ctx) \
TCGv_i32 t0, t1; \ TCGv_i32 t0, t1; \
TCGv_i64 t2; \ TCGv_i64 t2; \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
t0 = tcg_temp_new_i32(); \ t0 = tcg_temp_new_i32(); \
@ -7925,7 +7925,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@ -7936,7 +7936,7 @@ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
TCGv_i32 t0, t1; \ TCGv_i32 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
t0 = tcg_temp_new_i32(); \ t0 = tcg_temp_new_i32(); \
@ -7951,7 +7951,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
@ -7992,7 +7992,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
@ -8003,7 +8003,7 @@ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
TCGv_i64 t0, t1; \ TCGv_i64 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
t0 = tcg_temp_new_i64(); \ t0 = tcg_temp_new_i64(); \
@ -8019,7 +8019,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
@ -8030,7 +8030,7 @@ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
TCGv_i64 t0, t1; \ TCGv_i64 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \ if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \ return; \
} \ } \
t0 = tcg_temp_new_i64(); \ t0 = tcg_temp_new_i64(); \
@ -8052,7 +8052,7 @@ GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
static inline void gen_evfsabs(DisasContext *ctx) static inline void gen_evfsabs(DisasContext *ctx)
{ {
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
@ -8065,7 +8065,7 @@ static inline void gen_evfsabs(DisasContext *ctx)
static inline void gen_evfsnabs(DisasContext *ctx) static inline void gen_evfsnabs(DisasContext *ctx)
{ {
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
@ -8078,7 +8078,7 @@ static inline void gen_evfsnabs(DisasContext *ctx)
static inline void gen_evfsneg(DisasContext *ctx) static inline void gen_evfsneg(DisasContext *ctx)
{ {
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
@ -8134,7 +8134,7 @@ GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
static inline void gen_efsabs(DisasContext *ctx) static inline void gen_efsabs(DisasContext *ctx)
{ {
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
@ -8142,7 +8142,7 @@ static inline void gen_efsabs(DisasContext *ctx)
static inline void gen_efsnabs(DisasContext *ctx) static inline void gen_efsnabs(DisasContext *ctx)
{ {
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
@ -8150,7 +8150,7 @@ static inline void gen_efsnabs(DisasContext *ctx)
static inline void gen_efsneg(DisasContext *ctx) static inline void gen_efsneg(DisasContext *ctx)
{ {
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
@ -8202,7 +8202,7 @@ GEN_SPEFPUOP_ARITH2_64_64(efddiv);
static inline void gen_efdabs(DisasContext *ctx) static inline void gen_efdabs(DisasContext *ctx)
{ {
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
@ -8215,7 +8215,7 @@ static inline void gen_efdabs(DisasContext *ctx)
static inline void gen_efdnabs(DisasContext *ctx) static inline void gen_efdnabs(DisasContext *ctx)
{ {
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
@ -8228,7 +8228,7 @@ static inline void gen_efdnabs(DisasContext *ctx)
static inline void gen_efdneg(DisasContext *ctx) static inline void gen_efdneg(DisasContext *ctx)
{ {
if (unlikely(!ctx->spe_enabled)) { if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU); gen_exception(ctx, POWERPC_EXCP_SPEU);
return; return;
} }
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)