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hw/arm_gic: Move CPU interface memory region setup into arm_gic_init

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Remove more NVIC ifdefs by moving the code to setup the CPU interface
memory regions into the GIC specific arm_gic_init() function rather
than the gic_init() function. Rename the latter to more closely
reflect what it's now actually doing.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2012-05-02 16:49:41 +00:00
parent 84e4fccb7f
commit 2b518c56a6
2 changed files with 14 additions and 14 deletions
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26
hw/arm_gic.c
View File

@ -812,7 +812,7 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
static void gic_init(gic_state *s, int num_irq)
static void gic_init_irqs_and_distributor(gic_state *s, int num_irq)
{
int i;
@ -850,7 +850,19 @@ static void gic_init(gic_state *s, int num_irq)
sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
}
memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);
register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s);
}
#ifndef NVIC
static int arm_gic_init(SysBusDevice *dev)
{
/* Device instance init function for the GIC sysbus device */
int i;
gic_state *s = FROM_SYSBUS(gic_state, dev);
gic_init_irqs_and_distributor(s, s->num_irq);
/* Memory regions for the CPU interfaces (NVIC doesn't have these):
* a region for "CPU interface for this core", then a region for
* "CPU interface for core 0", "for core 1", ...
@ -866,19 +878,7 @@ static void gic_init(gic_state *s, int num_irq)
memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i],
"gic_cpu", 0x100);
}
#endif
register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s);
}
#ifndef NVIC
static int arm_gic_init(SysBusDevice *dev)
{
/* Device instance init function for the GIC sysbus device */
int i;
gic_state *s = FROM_SYSBUS(gic_state, dev);
gic_init(s, s->num_irq);
/* Distributor */
sysbus_init_mmio(dev, &s->iomem);
/* cpu interfaces (one for "current cpu" plus one per cpu) */

2
hw/armv7m_nvic.c
View File

@ -449,7 +449,7 @@ static int armv7m_nvic_init(SysBusDevice *dev)
s->gic.num_cpu = 1;
/* Tell the common code we're an NVIC */
s->gic.revision = 0xffffffff;
gic_init(&s->gic, s->num_irq);
gic_init_irqs_and_distributor(&s->gic, s->num_irq);
/* The NVIC and system controller register area looks like this:
* 0..0xff : system control registers, including systick
* 0x100..0xcff : GIC-like registers