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hw/timer/pxa2xx_timer: replace hw_error() -> qemu_log_mask()
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 20180103224208.30291-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -13,6 +13,7 @@
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#include "sysemu/sysemu.h"
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#include "hw/arm/pxa.h"
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#include "hw/sysbus.h"
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#include "qemu/log.h"
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#define OSMR0 0x00
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#define OSMR1 0x04
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@ -252,8 +253,14 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
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case OSNR:
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return s->snapshot;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s: unknown register 0x%02" HWADDR_PRIx "\n",
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__func__, offset);
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break;
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badreg:
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hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: incorrect register 0x%02" HWADDR_PRIx "\n",
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__func__, offset);
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}
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return 0;
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@ -377,8 +384,14 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset,
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}
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s: unknown register 0x%02" HWADDR_PRIx " "
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"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
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break;
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badreg:
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hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: incorrect register 0x%02" HWADDR_PRIx " "
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"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
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}
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}
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