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MIPS patches 2015-07-16
Changes: * bug fixes -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJVp2WoAAoJEFIRjjwLKdprb6IH/2LjKE10eFTn6M08glegVKMc 8yt/Ba212lKnAMnp57L2iqL3zjTHgYofKc0iThqopBWpiS6+2UhlXSukExKcNcZ2 8UgvR89zvEqadKchv64EXcKh+K8/ylMPPDkuf9UZJOGt+YQncdvGPNw/vqaCeEqj tUQQNyDITs/+JCaMksNtIURgrkOqCprOvI4/wYxvZUJjecSrN9kpmv1NI3Cmqwlw SlQ+HjecHNEms50C6T12OhQprNuuwEb+nOysWoJjldkWeayAuTmCg7g89flF9wu9 dE0xZN3XtAVxmW9stTqHp0IwO3mwFAw13CZxiZ7dnT0rx5KGaq9nj53qlIqG9L0= =dHki -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150716' into staging MIPS patches 2015-07-16 Changes: * bug fixes # gpg: Signature made Thu Jul 16 09:04:56 2015 BST using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20150716: target-mips: fix page fault address for LWL/LWR/LDL/LDR linux-user: Fix MIPS N64 trap and break instruction bug target-mips: fix resource leak reported by Coverity target-mips: fix logically dead code reported by Coverity target-mips: correct DERET instruction target-mips: fix ASID synchronisation for MIPS MT disas/mips: fix disassembling R6 instructions target-mips: fix to clear MSACSR.Cause target-mips: fix MIPS64R6-generic configuration Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
2d5ee9e7a7
12
disas/mips.c
12
disas/mips.c
@ -1296,12 +1296,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"dmod", "d,s,t", 0x000000de, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
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{"ddivu", "d,s,t", 0x0000009f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
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{"dmodu", "d,s,t", 0x000000df, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
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{"ll", "t,o(b)", 0x7c000036, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6},
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{"sc", "t,o(b)", 0x7c000026, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6},
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{"lld", "t,o(b)", 0x7c000037, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6},
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{"scd", "t,o(b)", 0x7c000027, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6},
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{"pref", "h,o(b)", 0x7c000035, 0xfc00007f, RD_b, 0, I32R6},
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{"cache", "k,o(b)", 0x7c000025, 0xfc00007f, RD_b, 0, I32R6},
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{"ll", "t,+o(b)", 0x7c000036, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6},
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{"sc", "t,+o(b)", 0x7c000026, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6},
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{"lld", "t,+o(b)", 0x7c000037, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6},
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{"scd", "t,+o(b)", 0x7c000027, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6},
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{"pref", "h,+o(b)", 0x7c000035, 0xfc00007f, RD_b, 0, I32R6},
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{"cache", "k,+o(b)", 0x7c000025, 0xfc00007f, RD_b, 0, I32R6},
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{"seleqz", "d,v,t", 0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
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{"selnez", "d,v,t", 0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
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{"maddf.s", "D,S,T", 0x46000018, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
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@ -2577,7 +2577,7 @@ done_syscall:
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code = (trap_instr >> 6) & 0x3f;
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}
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} else {
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ret = get_user_ual(trap_instr, env->active_tc.PC);
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ret = get_user_u32(trap_instr, env->active_tc.PC);
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if (ret != 0) {
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goto error;
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}
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@ -2611,7 +2611,7 @@ done_syscall:
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trap_instr = (instr[0] << 16) | instr[1];
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} else {
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ret = get_user_ual(trap_instr, env->active_tc.PC);
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ret = get_user_u32(trap_instr, env->active_tc.PC);
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}
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if (ret != 0) {
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@ -11,7 +11,7 @@
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#if defined(TARGET_MIPS64)
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#define TARGET_LONG_BITS 64
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#define TARGET_PHYS_ADDR_SPACE_BITS 48
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#define TARGET_VIRT_ADDR_SPACE_BITS 42
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#define TARGET_VIRT_ADDR_SPACE_BITS 48
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#else
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#define TARGET_LONG_BITS 32
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#define TARGET_PHYS_ADDR_SPACE_BITS 40
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@ -220,6 +220,23 @@ static int copy_argn_to_target(CPUMIPSState *env, int arg_num,
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} \
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} while (0)
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#define GET_TARGET_STRINGS_2(p, addr, p2, addr2) \
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do { \
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p = lock_user_string(addr); \
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if (!p) { \
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gpr[2] = -1; \
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gpr[3] = EFAULT; \
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goto uhi_done; \
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} \
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p2 = lock_user_string(addr2); \
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if (!p2) { \
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unlock_user(p, addr, 0); \
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gpr[2] = -1; \
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gpr[3] = EFAULT; \
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goto uhi_done; \
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} \
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} while (0)
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#define FREE_TARGET_STRING(p, gpr) \
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do { \
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unlock_user(p, gpr, 0); \
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@ -322,8 +339,7 @@ void helper_do_semihosting(CPUMIPSState *env)
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FREE_TARGET_STRING(p, gpr[4]);
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break;
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case UHI_assert:
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GET_TARGET_STRING(p, gpr[4]);
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GET_TARGET_STRING(p2, gpr[5]);
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GET_TARGET_STRINGS_2(p, gpr[4], p2, gpr[5]);
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printf("assertion '");
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printf("\"%s\"", p);
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printf("': file \"%s\", line %d\n", p2, (int)gpr[6]);
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@ -341,8 +357,7 @@ void helper_do_semihosting(CPUMIPSState *env)
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break;
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#ifndef _WIN32
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case UHI_link:
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GET_TARGET_STRING(p, gpr[4]);
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GET_TARGET_STRING(p2, gpr[5]);
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GET_TARGET_STRINGS_2(p, gpr[4], p2, gpr[5]);
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gpr[2] = link(p, p2);
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gpr[3] = errno_mips(errno);
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FREE_TARGET_STRING(p2, gpr[5]);
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@ -2642,6 +2642,8 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
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wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
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uint32_t i;
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clear_msacsr_cause(env);
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switch (df) {
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case DF_WORD:
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for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
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@ -3192,6 +3194,8 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
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wr_t *pws = &(env->active_fpu.fpr[ws].wr);
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uint32_t i;
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clear_msacsr_cause(env);
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switch (df) {
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case DF_WORD:
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for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
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@ -3224,6 +3228,8 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
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wr_t *pws = &(env->active_fpu.fpr[ws].wr);
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uint32_t i;
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clear_msacsr_cause(env);
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switch (df) {
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case DF_WORD:
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for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
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@ -661,7 +661,7 @@ static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
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/* Sync the TASID with EntryHi. */
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cpu->CP0_EntryHi &= ~0xff;
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cpu->CP0_EntryHi = tasid;
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cpu->CP0_EntryHi |= tasid;
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compute_hflags(cpu);
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}
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@ -2154,10 +2154,9 @@ void helper_deret(CPUMIPSState *env)
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debug_pre_eret(env);
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set_pc(env, env->CP0_DEPC);
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env->hflags &= MIPS_HFLAG_DM;
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env->hflags &= ~MIPS_HFLAG_DM;
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compute_hflags(env);
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debug_post_eret(env);
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env->lladdr = 1;
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}
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#endif /* !CONFIG_USER_ONLY */
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@ -2142,6 +2142,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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break;
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case OPC_LDL:
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t1 = tcg_temp_new();
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/* Do a byte access to possibly trigger a page
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fault with the unaligned address. */
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tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
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tcg_gen_andi_tl(t1, t0, 7);
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#ifndef TARGET_WORDS_BIGENDIAN
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tcg_gen_xori_tl(t1, t1, 7);
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@ -2163,6 +2166,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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break;
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case OPC_LDR:
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t1 = tcg_temp_new();
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/* Do a byte access to possibly trigger a page
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fault with the unaligned address. */
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tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
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tcg_gen_andi_tl(t1, t0, 7);
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#ifdef TARGET_WORDS_BIGENDIAN
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tcg_gen_xori_tl(t1, t1, 7);
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@ -2229,6 +2235,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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break;
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case OPC_LWL:
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t1 = tcg_temp_new();
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/* Do a byte access to possibly trigger a page
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fault with the unaligned address. */
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tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
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tcg_gen_andi_tl(t1, t0, 3);
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#ifndef TARGET_WORDS_BIGENDIAN
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tcg_gen_xori_tl(t1, t1, 3);
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@ -2251,6 +2260,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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break;
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case OPC_LWR:
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t1 = tcg_temp_new();
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/* Do a byte access to possibly trigger a page
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fault with the unaligned address. */
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tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
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tcg_gen_andi_tl(t1, t0, 3);
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#ifdef TARGET_WORDS_BIGENDIAN
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tcg_gen_xori_tl(t1, t1, 3);
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@ -9552,6 +9564,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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gen_cmp_s(ctx, func-48, ft, fs, cc);
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opn = condnames[func-48];
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}
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optype = CMPOP;
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break;
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case OPC_ADD_D:
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check_cp1_registers(ctx, fs | ft | fd);
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@ -10036,6 +10049,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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gen_cmp_d(ctx, func-48, ft, fs, cc);
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opn = condnames[func-48];
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}
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optype = CMPOP;
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break;
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case OPC_CVT_S_D:
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check_cp1_registers(ctx, fs);
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@ -10461,6 +10475,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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gen_cmp_ps(ctx, func-48, ft, fs, cc);
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opn = condnames[func-48];
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}
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optype = CMPOP;
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break;
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default:
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MIPS_INVAL(opn);
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@ -655,14 +655,14 @@ static const mips_def_t mips_defs[] =
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(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
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(0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) |
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(1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << CP0C3_LPA) |
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(1U << CP0C3_M),
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.CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
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(3 << CP0C4_IE) | (1 << CP0C4_M),
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.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
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(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
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(1 << CP0C3_RXI) | (1 << CP0C3_LPA),
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.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
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(0xfc << CP0C4_KScrExist),
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.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB),
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.CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
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(1 << CP0C5_UFE),
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.CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
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(1 << CP0C5_FRE) | (1 << CP0C5_UFE),
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 0,
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.SYNCI_Step = 32,
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@ -674,9 +674,9 @@ static const mips_def_t mips_defs[] =
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.CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) |
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(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
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(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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.SEGBITS = 42,
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.SEGBITS = 48,
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.PABITS = 48,
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.insn_flags = CPU_MIPS64R6,
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.insn_flags = CPU_MIPS64R6 | ASE_MSA,
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.mmu_type = MMU_TYPE_R4000,
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},
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{
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