mirror of
https://github.com/xemu-project/xemu.git
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consistent use of target_ulong and target_phys_addr_t
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@758 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
52c00a5f15
commit
2e12669a4c
23
cpu-all.h
23
cpu-all.h
@ -620,8 +620,8 @@ extern int code_copy_enabled;
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#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
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void cpu_interrupt(CPUState *s, int mask);
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int cpu_breakpoint_insert(CPUState *env, uint32_t pc);
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int cpu_breakpoint_remove(CPUState *env, uint32_t pc);
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int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
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int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
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void cpu_single_step(CPUState *env, int enabled);
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/* Return the physical page corresponding to a virtual one. Use it
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@ -681,24 +681,25 @@ extern uint8_t *phys_ram_dirty;
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#define IO_MEM_CODE (3 << IO_MEM_SHIFT) /* used internally, never use directly */
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#define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */
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typedef void CPUWriteMemoryFunc(uint32_t addr, uint32_t value);
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typedef uint32_t CPUReadMemoryFunc(uint32_t addr);
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typedef void CPUWriteMemoryFunc(target_phys_addr_t addr, uint32_t value);
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typedef uint32_t CPUReadMemoryFunc(target_phys_addr_t addr);
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void cpu_register_physical_memory(unsigned long start_addr, unsigned long size,
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long phys_offset);
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void cpu_register_physical_memory(target_phys_addr_t start_addr,
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unsigned long size,
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unsigned long phys_offset);
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int cpu_register_io_memory(int io_index,
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CPUReadMemoryFunc **mem_read,
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CPUWriteMemoryFunc **mem_write);
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void cpu_physical_memory_rw(target_ulong addr, uint8_t *buf,
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void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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int len, int is_write);
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static inline void cpu_physical_memory_read(target_ulong addr, uint8_t *buf,
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int len)
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static inline void cpu_physical_memory_read(target_phys_addr_t addr,
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uint8_t *buf, int len)
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{
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cpu_physical_memory_rw(addr, buf, len, 0);
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}
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static inline void cpu_physical_memory_write(target_ulong addr, const uint8_t *buf,
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int len)
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static inline void cpu_physical_memory_write(target_phys_addr_t addr,
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const uint8_t *buf, int len)
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{
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cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
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}
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20
exec-all.h
20
exec-all.h
@ -86,13 +86,16 @@ int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
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int cpu_restore_state_copy(struct TranslationBlock *tb,
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CPUState *env, unsigned long searched_pc,
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void *puc);
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void cpu_resume_from_signal(CPUState *env1, void *puc);
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void cpu_exec_init(void);
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int page_unprotect(unsigned long address);
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int page_unprotect(unsigned long address, unsigned long pc, void *puc);
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void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
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int is_cpu_write_access);
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void tb_invalidate_page_range(target_ulong start, target_ulong end);
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void tlb_flush_page(CPUState *env, uint32_t addr);
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void tlb_flush_page_write(CPUState *env, uint32_t addr);
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void tlb_flush_page(CPUState *env, target_ulong addr);
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void tlb_flush(CPUState *env, int flush_global);
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int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot,
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int tlb_set_page(CPUState *env, target_ulong vaddr,
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target_phys_addr_t paddr, int prot,
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int is_user, int is_softmmu);
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#define CODE_GEN_MAX_SIZE 65536
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@ -146,8 +149,8 @@ int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot,
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#endif
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typedef struct TranslationBlock {
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unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */
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unsigned long cs_base; /* CS base for this block */
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target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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target_ulong cs_base; /* CS base for this block */
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unsigned int flags; /* flags defining in which context the code was generated */
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uint16_t size; /* size of target code for this block (1 <=
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size <= TARGET_PAGE_SIZE) */
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@ -155,6 +158,7 @@ typedef struct TranslationBlock {
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#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
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#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
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#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
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#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
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uint8_t *tc_ptr; /* pointer to the translated code */
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struct TranslationBlock *hash_next; /* next matching tb for virtual address */
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@ -206,8 +210,8 @@ extern uint8_t *code_gen_ptr;
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/* find a translation block in the translation cache. If not found,
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return NULL and the pointer to the last element of the list in pptb */
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static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
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unsigned long pc,
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unsigned long cs_base,
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target_ulong pc,
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target_ulong cs_base,
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unsigned int flags)
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{
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TranslationBlock **ptb, *tb;
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42
exec.c
42
exec.c
@ -64,7 +64,7 @@ uint8_t *phys_ram_base;
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uint8_t *phys_ram_dirty;
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typedef struct PageDesc {
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/* offset in memory of the page + io_index in the low 12 bits */
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/* offset in host memory of the page + io_index in the low 12 bits */
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unsigned long phys_offset;
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/* list of TBs intersecting this physical page */
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TranslationBlock *first_tb;
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@ -1011,7 +1011,7 @@ static void breakpoint_invalidate(CPUState *env, target_ulong pc)
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/* add a breakpoint. EXCP_DEBUG is returned by the CPU loop if a
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breakpoint is reached */
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int cpu_breakpoint_insert(CPUState *env, uint32_t pc)
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int cpu_breakpoint_insert(CPUState *env, target_ulong pc)
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{
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#if defined(TARGET_I386) || defined(TARGET_PPC)
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int i;
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@ -1033,7 +1033,7 @@ int cpu_breakpoint_insert(CPUState *env, uint32_t pc)
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}
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/* remove a breakpoint */
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int cpu_breakpoint_remove(CPUState *env, uint32_t pc)
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int cpu_breakpoint_remove(CPUState *env, target_ulong pc)
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{
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#if defined(TARGET_I386) || defined(TARGET_PPC)
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int i;
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@ -1221,7 +1221,7 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, uint32_t addr)
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tlb_entry->address = -1;
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}
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void tlb_flush_page(CPUState *env, uint32_t addr)
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void tlb_flush_page(CPUState *env, target_ulong addr)
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{
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int i, n;
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VirtPageDesc *vp;
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@ -1415,7 +1415,8 @@ static inline void tlb_set_dirty(unsigned long addr, target_ulong vaddr)
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is permitted. Return 0 if OK or 2 if the page could not be mapped
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(can only happen in non SOFTMMU mode for I/O pages or pages
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conflicting with the host address space). */
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int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot,
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int tlb_set_page(CPUState *env, target_ulong vaddr,
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target_phys_addr_t paddr, int prot,
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int is_user, int is_softmmu)
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{
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PageDesc *p;
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@ -1583,15 +1584,12 @@ void tlb_flush(CPUState *env, int flush_global)
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{
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}
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void tlb_flush_page(CPUState *env, uint32_t addr)
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void tlb_flush_page(CPUState *env, target_ulong addr)
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{
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}
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void tlb_flush_page_write(CPUState *env, uint32_t addr)
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{
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}
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int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot,
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int tlb_set_page(CPUState *env, target_ulong vaddr,
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target_phys_addr_t paddr, int prot,
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int is_user, int is_softmmu)
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{
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return 0;
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@ -1739,8 +1737,9 @@ static inline void tlb_set_dirty(unsigned long addr, target_ulong vaddr)
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/* register physical memory. 'size' must be a multiple of the target
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page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
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io memory page */
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void cpu_register_physical_memory(unsigned long start_addr, unsigned long size,
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long phys_offset)
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void cpu_register_physical_memory(target_phys_addr_t start_addr,
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unsigned long size,
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unsigned long phys_offset)
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{
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unsigned long addr, end_addr;
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PageDesc *p;
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@ -1754,12 +1753,12 @@ void cpu_register_physical_memory(unsigned long start_addr, unsigned long size,
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}
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}
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static uint32_t unassigned_mem_readb(uint32_t addr)
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static uint32_t unassigned_mem_readb(target_phys_addr_t addr)
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{
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return 0;
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}
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static void unassigned_mem_writeb(uint32_t addr, uint32_t val)
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static void unassigned_mem_writeb(target_phys_addr_t addr, uint32_t val)
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{
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}
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@ -1778,7 +1777,7 @@ static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
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/* self modifying code support in soft mmu mode : writing to a page
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containing code comes to these functions */
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static void code_mem_writeb(uint32_t addr, uint32_t val)
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static void code_mem_writeb(target_phys_addr_t addr, uint32_t val)
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{
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unsigned long phys_addr;
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@ -1790,7 +1789,7 @@ static void code_mem_writeb(uint32_t addr, uint32_t val)
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phys_ram_dirty[phys_addr >> TARGET_PAGE_BITS] = 1;
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}
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static void code_mem_writew(uint32_t addr, uint32_t val)
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static void code_mem_writew(target_phys_addr_t addr, uint32_t val)
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{
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unsigned long phys_addr;
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@ -1802,7 +1801,7 @@ static void code_mem_writew(uint32_t addr, uint32_t val)
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phys_ram_dirty[phys_addr >> TARGET_PAGE_BITS] = 1;
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}
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static void code_mem_writel(uint32_t addr, uint32_t val)
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static void code_mem_writel(target_phys_addr_t addr, uint32_t val)
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{
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unsigned long phys_addr;
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@ -1892,7 +1891,7 @@ int cpu_register_io_memory(int io_index,
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/* physical memory access (slow version, mainly for debug) */
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#if defined(CONFIG_USER_ONLY)
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void cpu_physical_memory_rw(target_ulong addr, uint8_t *buf,
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void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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int len, int is_write)
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{
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int l, flags;
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@ -1921,13 +1920,14 @@ void cpu_physical_memory_rw(target_ulong addr, uint8_t *buf,
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}
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}
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#else
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void cpu_physical_memory_rw(target_ulong addr, uint8_t *buf,
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void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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int len, int is_write)
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{
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int l, io_index;
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uint8_t *ptr;
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uint32_t val;
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target_ulong page, pd;
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target_phys_addr_t page;
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unsigned long pd;
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PageDesc *p;
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while (len > 0) {
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@ -104,7 +104,7 @@ static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
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/* IO ports emulation */
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#define PPC_IO_BASE 0x80000000
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static void PPC_io_writeb (uint32_t addr, uint32_t value, uint32_t vaddr)
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static void PPC_io_writeb (target_phys_addr_t addr, uint32_t value)
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{
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/* Don't polute serial port output */
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#if 0
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@ -121,7 +121,7 @@ static void PPC_io_writeb (uint32_t addr, uint32_t value, uint32_t vaddr)
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cpu_outb(NULL, addr - PPC_IO_BASE, value);
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}
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static uint32_t PPC_io_readb (uint32_t addr)
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static uint32_t PPC_io_readb (target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inb(NULL, addr - PPC_IO_BASE);
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@ -141,7 +141,7 @@ static uint32_t PPC_io_readb (uint32_t addr)
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return ret;
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}
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static void PPC_io_writew (uint32_t addr, uint32_t value, uint32_t vaddr)
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static void PPC_io_writew (target_phys_addr_t addr, uint32_t value)
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{
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if ((addr < 0x800001f0 || addr > 0x800001f7) &&
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(addr < 0x80000170 || addr > 0x80000177)) {
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@ -150,7 +150,7 @@ static void PPC_io_writew (uint32_t addr, uint32_t value, uint32_t vaddr)
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cpu_outw(NULL, addr - PPC_IO_BASE, value);
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}
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static uint32_t PPC_io_readw (uint32_t addr)
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static uint32_t PPC_io_readw (target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inw(NULL, addr - PPC_IO_BASE);
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@ -162,13 +162,13 @@ static uint32_t PPC_io_readw (uint32_t addr)
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return ret;
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}
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static void PPC_io_writel (uint32_t addr, uint32_t value, uint32_t vaddr)
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static void PPC_io_writel (target_phys_addr_t addr, uint32_t value)
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{
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PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr - PPC_IO_BASE, value);
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cpu_outl(NULL, addr - PPC_IO_BASE, value);
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}
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static uint32_t PPC_io_readl (uint32_t addr)
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static uint32_t PPC_io_readl (target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inl(NULL, addr - PPC_IO_BASE);
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@ -190,12 +190,12 @@ static CPUReadMemoryFunc *PPC_io_read[] = {
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};
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/* Read-only register (?) */
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static void _PPC_ioB_write (uint32_t addr, uint32_t value, uint32_t vaddr)
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static void _PPC_ioB_write (target_phys_addr_t addr, uint32_t value)
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{
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// printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
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}
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static uint32_t _PPC_ioB_read (uint32_t addr)
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static uint32_t _PPC_ioB_read (target_phys_addr_t addr)
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{
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uint32_t retval = 0;
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@ -636,9 +636,9 @@ static void VGA_printf (uint8_t *s)
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for (i = 0; i < format_width; i++) {
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nibble = (arg >> (4 * digit)) & 0x000f;
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if (nibble <= 9)
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PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + '0', 0);
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PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + '0');
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else
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PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + 'A', 0);
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PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + 'A');
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digit--;
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}
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in_format = 0;
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@ -647,7 +647,7 @@ static void VGA_printf (uint8_t *s)
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// in_format = 0;
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// }
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} else {
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PPC_io_writeb(PPC_IO_BASE + 0x500, c, 0);
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PPC_io_writeb(PPC_IO_BASE + 0x500, c);
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}
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s++;
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}
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@ -659,10 +659,10 @@ static void VGA_init (void)
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printf("Init VGA...\n");
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#if 1
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/* switch to color mode and enable CPU access 480 lines */
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PPC_io_writeb(PPC_IO_BASE + 0x3C2, 0xC3, 0);
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PPC_io_writeb(PPC_IO_BASE + 0x3C2, 0xC3);
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/* more than 64k 3C4/04 */
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PPC_io_writeb(PPC_IO_BASE + 0x3C4, 0x04, 0);
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PPC_io_writeb(PPC_IO_BASE + 0x3C5, 0x02, 0);
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PPC_io_writeb(PPC_IO_BASE + 0x3C4, 0x04);
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PPC_io_writeb(PPC_IO_BASE + 0x3C5, 0x02);
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#endif
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VGA_printf("PPC VGA BIOS...\n");
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}
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@ -690,7 +690,7 @@ void PPC_init_hw (/*CPUPPCState *env,*/ uint32_t mem_size,
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{
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#if 1
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uint32_t offset =
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*((uint32_t *)((uint32_t)phys_ram_base + kernel_addr));
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*((uint32_t *)(phys_ram_base + kernel_addr));
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#else
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uint32_t offset = 12;
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#endif
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@ -816,7 +816,7 @@ void PPC_init_hw (/*CPUPPCState *env,*/ uint32_t mem_size,
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{
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#if 0
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uint32_t offset =
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*((uint32_t *)((uint32_t)phys_ram_base + kernel_addr));
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*((uint32_t *)(phys_ram_base + kernel_addr));
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#else
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uint32_t offset = 12;
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#endif
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12
hw/vga.c
12
hw/vga.c
@ -648,7 +648,7 @@ static void vbe_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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#endif
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/* called for accesses between 0xa0000 and 0xc0000 */
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static uint32_t vga_mem_readb(uint32_t addr)
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static uint32_t vga_mem_readb(target_phys_addr_t addr)
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{
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VGAState *s = &vga_state;
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int memory_map_mode, plane;
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@ -704,7 +704,7 @@ static uint32_t vga_mem_readb(uint32_t addr)
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return ret;
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}
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|
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static uint32_t vga_mem_readw(uint32_t addr)
|
||||
static uint32_t vga_mem_readw(target_phys_addr_t addr)
|
||||
{
|
||||
uint32_t v;
|
||||
v = vga_mem_readb(addr);
|
||||
@ -712,7 +712,7 @@ static uint32_t vga_mem_readw(uint32_t addr)
|
||||
return v;
|
||||
}
|
||||
|
||||
static uint32_t vga_mem_readl(uint32_t addr)
|
||||
static uint32_t vga_mem_readl(target_phys_addr_t addr)
|
||||
{
|
||||
uint32_t v;
|
||||
v = vga_mem_readb(addr);
|
||||
@ -723,7 +723,7 @@ static uint32_t vga_mem_readl(uint32_t addr)
|
||||
}
|
||||
|
||||
/* called for accesses between 0xa0000 and 0xc0000 */
|
||||
static void vga_mem_writeb(uint32_t addr, uint32_t val)
|
||||
static void vga_mem_writeb(target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
VGAState *s = &vga_state;
|
||||
int memory_map_mode, plane, write_mode, b, func_select;
|
||||
@ -851,13 +851,13 @@ static void vga_mem_writeb(uint32_t addr, uint32_t val)
|
||||
}
|
||||
}
|
||||
|
||||
static void vga_mem_writew(uint32_t addr, uint32_t val)
|
||||
static void vga_mem_writew(target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
vga_mem_writeb(addr, val & 0xff);
|
||||
vga_mem_writeb(addr + 1, (val >> 8) & 0xff);
|
||||
}
|
||||
|
||||
static void vga_mem_writel(uint32_t addr, uint32_t val)
|
||||
static void vga_mem_writel(target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
vga_mem_writeb(addr, val & 0xff);
|
||||
vga_mem_writeb(addr + 1, (val >> 8) & 0xff);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user