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hw/timer/sh_timer: Coding style clean-up
Replace TAB characters with spaces, put code after case-statement on separate lines and add some curly braces in related lines to keep checkpatch.pl happy. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201020153935.54315-2-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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@ -118,34 +118,54 @@ static void sh_timer_write(void *opaque, hwaddr offset,
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case 3: freq >>= 8; break;
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case 4: freq >>= 10; break;
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case 6:
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case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
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default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
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case 7:
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if (s->feat & TIMER_FEAT_EXTCLK) {
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break;
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}
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default:
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hw_error("sh_timer_write: Reserved TPSC value\n");
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break;
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}
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switch ((value & TIMER_TCR_CKEG) >> 3) {
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case 0: break;
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case 0:
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break;
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case 1:
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case 2:
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case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
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default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
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case 3:
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if (s->feat & TIMER_FEAT_EXTCLK) {
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break;
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}
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default:
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hw_error("sh_timer_write: Reserved CKEG value\n");
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break;
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}
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switch ((value & TIMER_TCR_ICPE) >> 6) {
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case 0: break;
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case 0:
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break;
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case 2:
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case 3: if (s->feat & TIMER_FEAT_CAPT) break;
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default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
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case 3:
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if (s->feat & TIMER_FEAT_CAPT) {
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break;
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}
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if ((value & TIMER_TCR_UNF) == 0)
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default:
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hw_error("sh_timer_write: Reserved ICPE value\n");
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break;
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}
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if ((value & TIMER_TCR_UNF) == 0) {
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s->int_level = 0;
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}
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value &= ~TIMER_TCR_UNF;
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if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
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if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) {
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hw_error("sh_timer_write: Reserved ICPF value\n");
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}
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value &= ~TIMER_TCR_ICPF; /* capture not supported */
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if (value & TIMER_TCR_RESERVED)
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if (value & TIMER_TCR_RESERVED) {
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hw_error("sh_timer_write: Reserved TCR bits set\n");
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}
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s->tcr = value;
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ptimer_set_limit(s->timer, s->tcor, 0);
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ptimer_set_freq(s->timer, freq);
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@ -241,8 +261,9 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset,
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#endif
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if (offset >= 0x20) {
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if (!(s->feat & TMU012_FEAT_3CHAN))
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if (!(s->feat & TMU012_FEAT_3CHAN)) {
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hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
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}
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return sh_timer_read(s->timer[2], offset - 0x20);
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}
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@ -272,8 +293,9 @@ static void tmu012_write(void *opaque, hwaddr offset,
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#endif
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if (offset >= 0x20) {
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if (!(s->feat & TMU012_FEAT_3CHAN))
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if (!(s->feat & TMU012_FEAT_3CHAN)) {
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hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
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}
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sh_timer_write(s->timer[2], offset - 0x20, value);
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return;
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}
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@ -291,11 +313,13 @@ static void tmu012_write(void *opaque, hwaddr offset,
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if (offset == 4) {
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sh_timer_start_stop(s->timer[0], value & (1 << 0));
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sh_timer_start_stop(s->timer[1], value & (1 << 1));
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if (s->feat & TMU012_FEAT_3CHAN)
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if (s->feat & TMU012_FEAT_3CHAN) {
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sh_timer_start_stop(s->timer[2], value & (1 << 2));
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else
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if (value & (1 << 2))
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} else {
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if (value & (1 << 2)) {
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hw_error("tmu012_write: Bad channel\n");
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}
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}
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s->tstr = value;
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return;
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@ -324,9 +348,10 @@ void tmu012_init(MemoryRegion *sysmem, hwaddr base,
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s->feat = feat;
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s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
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s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
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if (feat & TMU012_FEAT_3CHAN)
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if (feat & TMU012_FEAT_3CHAN) {
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s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
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ch2_irq0); /* ch2_irq1 not supported */
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}
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memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
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"timer", 0x100000000ULL);
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