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target/arm: Rearrange disas_data_proc_reg
This decoding more closely matches the ARMv8.4 Table C4-6, Encoding table for Data Processing - Register Group. In particular, op2 == 0 is now more than just Add/sub (with carry). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190301200501.16533-7-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -4494,11 +4494,10 @@ static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
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}
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/* Add/subtract (with carry)
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* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
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* +--+--+--+------------------------+------+---------+------+-----+
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* |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
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* +--+--+--+------------------------+------+---------+------+-----+
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* [000000]
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* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
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* +--+--+--+------------------------+------+-------------+------+-----+
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* |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
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* +--+--+--+------------------------+------+-------------+------+-----+
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*/
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static void disas_adc_sbc(DisasContext *s, uint32_t insn)
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@ -4506,11 +4505,6 @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
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unsigned int sf, op, setflags, rm, rn, rd;
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TCGv_i64 tcg_y, tcg_rn, tcg_rd;
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if (extract32(insn, 10, 6) != 0) {
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unallocated_encoding(s);
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return;
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}
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sf = extract32(insn, 31, 1);
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op = extract32(insn, 30, 1);
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setflags = extract32(insn, 29, 1);
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@ -5164,47 +5158,69 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
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}
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}
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/* Data processing - register */
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/*
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* Data processing - register
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* 31 30 29 28 25 21 20 16 10 0
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* +--+---+--+---+-------+-----+-------+-------+---------+
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* | |op0| |op1| 1 0 1 | op2 | | op3 | |
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* +--+---+--+---+-------+-----+-------+-------+---------+
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*/
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static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
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{
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switch (extract32(insn, 24, 5)) {
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case 0x0a: /* Logical (shifted register) */
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disas_logic_reg(s, insn);
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break;
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case 0x0b: /* Add/subtract */
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if (insn & (1 << 21)) { /* (extended register) */
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disas_add_sub_ext_reg(s, insn);
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int op0 = extract32(insn, 30, 1);
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int op1 = extract32(insn, 28, 1);
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int op2 = extract32(insn, 21, 4);
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int op3 = extract32(insn, 10, 6);
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if (!op1) {
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if (op2 & 8) {
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if (op2 & 1) {
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/* Add/sub (extended register) */
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disas_add_sub_ext_reg(s, insn);
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} else {
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/* Add/sub (shifted register) */
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disas_add_sub_reg(s, insn);
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}
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} else {
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disas_add_sub_reg(s, insn);
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/* Logical (shifted register) */
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disas_logic_reg(s, insn);
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}
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break;
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case 0x1b: /* Data-processing (3 source) */
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disas_data_proc_3src(s, insn);
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break;
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case 0x1a:
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switch (extract32(insn, 21, 3)) {
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case 0x0: /* Add/subtract (with carry) */
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return;
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}
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switch (op2) {
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case 0x0:
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switch (op3) {
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case 0x00: /* Add/subtract (with carry) */
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disas_adc_sbc(s, insn);
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break;
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case 0x2: /* Conditional compare */
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disas_cc(s, insn); /* both imm and reg forms */
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break;
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case 0x4: /* Conditional select */
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disas_cond_select(s, insn);
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break;
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case 0x6: /* Data-processing */
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if (insn & (1 << 30)) { /* (1 source) */
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disas_data_proc_1src(s, insn);
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} else { /* (2 source) */
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disas_data_proc_2src(s, insn);
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}
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break;
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default:
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unallocated_encoding(s);
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break;
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goto do_unallocated;
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}
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break;
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case 0x2: /* Conditional compare */
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disas_cc(s, insn); /* both imm and reg forms */
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break;
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case 0x4: /* Conditional select */
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disas_cond_select(s, insn);
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break;
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case 0x6: /* Data-processing */
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if (op0) { /* (1 source) */
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disas_data_proc_1src(s, insn);
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} else { /* (2 source) */
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disas_data_proc_2src(s, insn);
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}
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break;
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case 0x8 ... 0xf: /* (3 source) */
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disas_data_proc_3src(s, insn);
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break;
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default:
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do_unallocated:
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unallocated_encoding(s);
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break;
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}
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