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irq: Introduce and use CPU_INTERRUPT_SSTEP_MASK.
This mask contains all of the bits that should be ignored while single stepping in the debugger. The mask contains 2 bits that are not currently cleared, but are also never set. The bits are included in the mask for consistency in handling of the CPU_INTERRUPT_TGT_EXT_N bits. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -837,6 +837,14 @@ extern CPUState *cpu_single_env;
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#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2
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#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
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/* The set of all bits that should be masked when single-stepping. */
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#define CPU_INTERRUPT_SSTEP_MASK \
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(CPU_INTERRUPT_HARD \
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| CPU_INTERRUPT_TGT_EXT_0 \
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| CPU_INTERRUPT_TGT_EXT_1 \
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| CPU_INTERRUPT_TGT_EXT_2 \
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| CPU_INTERRUPT_TGT_EXT_3 \
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| CPU_INTERRUPT_TGT_EXT_4)
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#ifndef CONFIG_USER_ONLY
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typedef void (*CPUInterruptHandler)(CPUState *, int);
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@ -360,10 +360,7 @@ int cpu_exec(CPUState *env1)
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if (unlikely(interrupt_request)) {
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if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
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/* Mask out external interrupts for this step. */
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interrupt_request &= ~(CPU_INTERRUPT_HARD |
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CPU_INTERRUPT_FIQ |
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CPU_INTERRUPT_SMI |
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CPU_INTERRUPT_NMI);
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interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
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}
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if (interrupt_request & CPU_INTERRUPT_DEBUG) {
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env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
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