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IDE: Add register hints to tracing
Name the registers for tracing purposes. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20170901001502.29915-3-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
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@ -1185,13 +1185,37 @@ static void ide_clear_hob(IDEBus *bus)
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bus->ifs[1].select &= ~(1 << 7);
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}
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/* IOport [W]rite [R]egisters */
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enum ATA_IOPORT_WR {
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ATA_IOPORT_WR_DATA = 0,
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ATA_IOPORT_WR_FEATURES = 1,
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ATA_IOPORT_WR_SECTOR_COUNT = 2,
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ATA_IOPORT_WR_SECTOR_NUMBER = 3,
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ATA_IOPORT_WR_CYLINDER_LOW = 4,
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ATA_IOPORT_WR_CYLINDER_HIGH = 5,
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ATA_IOPORT_WR_DEVICE_HEAD = 6,
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ATA_IOPORT_WR_COMMAND = 7,
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ATA_IOPORT_WR_NUM_REGISTERS,
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};
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const char *ATA_IOPORT_WR_lookup[ATA_IOPORT_WR_NUM_REGISTERS] = {
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[ATA_IOPORT_WR_DATA] = "Data",
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[ATA_IOPORT_WR_FEATURES] = "Features",
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[ATA_IOPORT_WR_SECTOR_COUNT] = "Sector Count",
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[ATA_IOPORT_WR_SECTOR_NUMBER] = "Sector Number",
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[ATA_IOPORT_WR_CYLINDER_LOW] = "Cylinder Low",
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[ATA_IOPORT_WR_CYLINDER_HIGH] = "Cylinder High",
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[ATA_IOPORT_WR_DEVICE_HEAD] = "Device/Head",
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[ATA_IOPORT_WR_COMMAND] = "Command"
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};
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void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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IDEBus *bus = opaque;
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IDEState *s = idebus_active_if(bus);
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int reg_num = addr & 7;
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trace_ide_ioport_write(addr, val, bus, s);
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trace_ide_ioport_write(addr, ATA_IOPORT_WR_lookup[reg_num], val, bus, s);
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/* ignore writes to command block while busy with previous command */
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if (reg_num != 7 && (s->status & (BUSY_STAT|DRQ_STAT))) {
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@ -1201,43 +1225,43 @@ void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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switch (reg_num) {
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case 0:
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break;
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case 1:
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ide_clear_hob(bus);
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case ATA_IOPORT_WR_FEATURES:
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ide_clear_hob(bus);
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/* NOTE: data is written to the two drives */
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bus->ifs[0].hob_feature = bus->ifs[0].feature;
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bus->ifs[1].hob_feature = bus->ifs[1].feature;
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bus->ifs[0].hob_feature = bus->ifs[0].feature;
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bus->ifs[1].hob_feature = bus->ifs[1].feature;
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bus->ifs[0].feature = val;
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bus->ifs[1].feature = val;
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break;
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case 2:
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case ATA_IOPORT_WR_SECTOR_COUNT:
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ide_clear_hob(bus);
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bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
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bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
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bus->ifs[0].nsector = val;
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bus->ifs[1].nsector = val;
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break;
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case 3:
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case ATA_IOPORT_WR_SECTOR_NUMBER:
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ide_clear_hob(bus);
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bus->ifs[0].hob_sector = bus->ifs[0].sector;
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bus->ifs[1].hob_sector = bus->ifs[1].sector;
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bus->ifs[0].sector = val;
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bus->ifs[1].sector = val;
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break;
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case 4:
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case ATA_IOPORT_WR_CYLINDER_LOW:
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ide_clear_hob(bus);
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bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
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bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
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bus->ifs[0].lcyl = val;
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bus->ifs[1].lcyl = val;
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break;
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case 5:
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case ATA_IOPORT_WR_CYLINDER_HIGH:
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ide_clear_hob(bus);
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bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
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bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
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bus->ifs[0].hcyl = val;
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bus->ifs[1].hcyl = val;
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break;
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case 6:
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case ATA_IOPORT_WR_DEVICE_HEAD:
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/* FIXME: HOB readback uses bit 7 */
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bus->ifs[0].select = (val & ~0x10) | 0xa0;
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bus->ifs[1].select = (val | 0x10) | 0xa0;
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@ -1245,7 +1269,7 @@ void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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bus->unit = (val >> 4) & 1;
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break;
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default:
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case 7:
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case ATA_IOPORT_WR_COMMAND:
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/* command */
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ide_exec_cmd(bus, val);
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break;
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@ -2052,6 +2076,30 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val)
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}
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}
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/* IOport [R]ead [R]egisters */
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enum ATA_IOPORT_RR {
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ATA_IOPORT_RR_DATA = 0,
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ATA_IOPORT_RR_ERROR = 1,
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ATA_IOPORT_RR_SECTOR_COUNT = 2,
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ATA_IOPORT_RR_SECTOR_NUMBER = 3,
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ATA_IOPORT_RR_CYLINDER_LOW = 4,
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ATA_IOPORT_RR_CYLINDER_HIGH = 5,
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ATA_IOPORT_RR_DEVICE_HEAD = 6,
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ATA_IOPORT_RR_STATUS = 7,
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ATA_IOPORT_RR_NUM_REGISTERS,
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};
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const char *ATA_IOPORT_RR_lookup[ATA_IOPORT_RR_NUM_REGISTERS] = {
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[ATA_IOPORT_RR_DATA] = "Data",
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[ATA_IOPORT_RR_ERROR] = "Error",
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[ATA_IOPORT_RR_SECTOR_COUNT] = "Sector Count",
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[ATA_IOPORT_RR_SECTOR_NUMBER] = "Sector Number",
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[ATA_IOPORT_RR_CYLINDER_LOW] = "Cylinder Low",
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[ATA_IOPORT_RR_CYLINDER_HIGH] = "Cylinder High",
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[ATA_IOPORT_RR_DEVICE_HEAD] = "Device/Head",
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[ATA_IOPORT_RR_STATUS] = "Status"
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};
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uint32_t ide_ioport_read(void *opaque, uint32_t addr)
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{
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IDEBus *bus = opaque;
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@ -2064,10 +2112,10 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
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//hob = s->select & (1 << 7);
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hob = 0;
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switch (reg_num) {
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case 0:
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case ATA_IOPORT_RR_DATA:
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ret = 0xff;
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break;
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case 1:
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case ATA_IOPORT_RR_ERROR:
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if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
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(s != bus->ifs && !s->blk)) {
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ret = 0;
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@ -2077,7 +2125,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
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ret = s->hob_feature;
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}
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break;
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case 2:
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case ATA_IOPORT_RR_SECTOR_COUNT:
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if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
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ret = 0;
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} else if (!hob) {
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@ -2086,7 +2134,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
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ret = s->hob_nsector;
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}
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break;
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case 3:
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case ATA_IOPORT_RR_SECTOR_NUMBER:
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if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
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ret = 0;
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} else if (!hob) {
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@ -2095,7 +2143,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
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ret = s->hob_sector;
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}
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break;
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case 4:
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case ATA_IOPORT_RR_CYLINDER_LOW:
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if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
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ret = 0;
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} else if (!hob) {
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@ -2104,7 +2152,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
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ret = s->hob_lcyl;
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}
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break;
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case 5:
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case ATA_IOPORT_RR_CYLINDER_HIGH:
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if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
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ret = 0;
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} else if (!hob) {
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@ -2113,7 +2161,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
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ret = s->hob_hcyl;
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}
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break;
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case 6:
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case ATA_IOPORT_RR_DEVICE_HEAD:
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if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
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ret = 0;
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} else {
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@ -2121,7 +2169,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
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}
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break;
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default:
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case 7:
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case ATA_IOPORT_RR_STATUS:
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if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
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(s != bus->ifs && !s->blk)) {
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ret = 0;
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@ -2132,7 +2180,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
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break;
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}
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trace_ide_ioport_read(addr, ret, bus, s);
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trace_ide_ioport_read(addr, ATA_IOPORT_RR_lookup[reg_num], ret, bus, s);
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return ret;
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}
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@ -2,10 +2,10 @@
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# hw/ide/core.c
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# portio
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ide_ioport_read(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO rd @ 0x%"PRIx32"; val 0x%02"PRIx32"; bus %p IDEState %p"
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ide_ioport_write(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO wr @ 0x%"PRIx32"; val 0x%02"PRIx32"; bus %p IDEState %p"
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ide_status_read(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO rd @ 0x%"PRIx32" (Alt Status); val 0x%02"PRIx32"; bus %p; IDEState %p"
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ide_cmd_write(uint32_t addr, uint32_t val, void *bus) "IDE PIO wr @ 0x%"PRIx32" (Device Control); val 0x%02"PRIx32"; bus %p"
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ide_ioport_read(uint32_t addr, const char *reg, uint32_t val, void *bus, void *s) "IDE PIO rd @ 0x%"PRIx32" (%s); val 0x%02"PRIx32"; bus %p IDEState %p"
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ide_ioport_write(uint32_t addr, const char *reg, uint32_t val, void *bus, void *s) "IDE PIO wr @ 0x%"PRIx32" (%s); val 0x%02"PRIx32"; bus %p IDEState %p"
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ide_status_read(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO rd @ 0x%"PRIx32" (Alt Status); val 0x%02"PRIx32"; bus %p; IDEState %p"
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ide_cmd_write(uint32_t addr, uint32_t val, void *bus) "IDE PIO wr @ 0x%"PRIx32" (Device Control); val 0x%02"PRIx32"; bus %p"
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# misc
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ide_exec_cmd(void *bus, void *state, uint32_t cmd) "IDE exec cmd: bus %p; state %p; cmd 0x%02x"
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ide_cancel_dma_sync_buffered(void *fn, void *req) "invoking cb %p of buffered request %p with -ECANCELED"
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