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target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN

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Writes to AdvSIMD registers flush the bits above 128.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214194643.23317-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-02-14 11:46:42 -08:00 committed by Peter Maydell
parent 263273bc98
commit 33649de62e
1 changed files with 1 additions and 0 deletions
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target/arm/translate-a64.c
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@ -7054,6 +7054,7 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_resl);
write_vec_element(s, tcg_resh, rd, 1, MO_64);
tcg_temp_free_i64(tcg_resh);
clear_vec_high(s, true, rd);
}
/*