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aspeed_sdmc: Init status always idle

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The ast2500 SDRAM training routine busy waits on the 'init cycle busy
state' bit in DDR PHY Control/Status register #1 (MCR60).

This ensures the bit always reads zero, and allows training to
complete with upstream u-boot on the ast2500-evb.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20180807075757.7242-5-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Joel Stanley 2018-08-16 14:05:29 +01:00 committed by Peter Maydell
parent b33f1e0b89
commit 33883ce840
1 changed files with 15 additions and 0 deletions
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15
hw/misc/aspeed_sdmc.c
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@ -23,6 +23,10 @@
/* Configuration Register */
#define R_CONF (0x04 / 4)
/* Control/Status Register #1 (ast2500) */
#define R_STATUS1 (0x60 / 4)
#define PHY_BUSY_STATE BIT(0)
/*
* Configuration register Ox4 (for Aspeed AST2400 SOC)
*
@ -137,6 +141,17 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
g_assert_not_reached();
}
}
if (s->silicon_rev == AST2500_A0_SILICON_REV ||
s->silicon_rev == AST2500_A1_SILICON_REV) {
switch (addr) {
case R_STATUS1:
/* Will never return 'busy' */
data &= ~PHY_BUSY_STATE;
break;
default:
break;
}
}
s->regs[addr] = data;
}