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target-mips: implement forbidden slot
When conditional compact branch is encountered decode one more instruction in current translation block - that will be forbidden slot. Instruction in forbidden slot will be executed only if conditional compact branch is not taken. Any control transfer instruction (CTI) which are branches, jumps, ERET, DERET, WAIT and PAUSE will generate RI exception if executed in forbidden or delay slot. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
This commit is contained in:
Leon Alrae
parent
faf1f68ba1
commit
339cd2a82a
@ -488,7 +488,7 @@ struct CPUMIPSState {
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* the delay slot, record what type of branch it is so that we can
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* resume translation properly. It might be possible to reduce
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* this from three bits to two. */
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#define MIPS_HFLAG_BMASK_BASE 0x03800
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#define MIPS_HFLAG_BMASK_BASE 0x803800
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#define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
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#define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
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#define MIPS_HFLAG_BL 0x01800 /* Likely branch */
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@ -507,6 +507,7 @@ struct CPUMIPSState {
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/* Extra flag about HWREna register. */
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#define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
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#define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
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#define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */
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target_ulong btarget; /* Jump / branch target */
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target_ulong bcond; /* Branch condition (if needed) */
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@ -4136,7 +4136,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
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if (ctx->hflags & MIPS_HFLAG_BMASK) {
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#ifdef MIPS_DEBUG_DISAS
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LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc);
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LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
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TARGET_FMT_lx "\n", ctx->pc);
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#endif
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generate_exception(ctx, EXCP_RI);
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goto out;
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@ -7638,12 +7639,22 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
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case OPC_ERET:
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opn = "eret";
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check_insn(ctx, ISA_MIPS2);
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if ((ctx->insn_flags & ISA_MIPS32R6) &&
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(ctx->hflags & MIPS_HFLAG_BMASK)) {
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MIPS_DEBUG("CTI in delay / forbidden slot");
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goto die;
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}
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gen_helper_eret(cpu_env);
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ctx->bstate = BS_EXCP;
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break;
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case OPC_DERET:
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opn = "deret";
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check_insn(ctx, ISA_MIPS32);
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if ((ctx->insn_flags & ISA_MIPS32R6) &&
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(ctx->hflags & MIPS_HFLAG_BMASK)) {
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MIPS_DEBUG("CTI in delay / forbidden slot");
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goto die;
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}
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if (!(ctx->hflags & MIPS_HFLAG_DM)) {
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MIPS_INVAL(opn);
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generate_exception(ctx, EXCP_RI);
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@ -7655,6 +7666,11 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
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case OPC_WAIT:
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opn = "wait";
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check_insn(ctx, ISA_MIPS3 | ISA_MIPS32);
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if ((ctx->insn_flags & ISA_MIPS32R6) &&
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(ctx->hflags & MIPS_HFLAG_BMASK)) {
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MIPS_DEBUG("CTI in delay / forbidden slot");
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goto die;
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}
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/* If we get an exception, we want to restart at next instruction */
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ctx->pc += 4;
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save_cpu_state(ctx, 1);
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@ -7681,6 +7697,12 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
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const char *opn = "cp1 cond branch";
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TCGv_i32 t0 = tcg_temp_new_i32();
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if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) {
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MIPS_DEBUG("CTI in delay / forbidden slot");
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generate_exception(ctx, EXCP_RI);
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goto out;
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}
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if (cc != 0)
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check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
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@ -7797,7 +7819,8 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
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if (ctx->hflags & MIPS_HFLAG_BMASK) {
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#ifdef MIPS_DEBUG_DISAS
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LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc);
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LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
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"\n", ctx->pc);
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#endif
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generate_exception(ctx, EXCP_RI);
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goto out;
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@ -10251,6 +10274,10 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
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save_cpu_state(ctx, 0);
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/* FIXME: Need to clear can_do_io. */
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switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) {
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case MIPS_HFLAG_FBNSLOT:
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MIPS_DEBUG("forbidden slot");
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gen_goto_tb(ctx, 0, ctx->pc + insn_bytes);
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break;
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case MIPS_HFLAG_B:
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/* unconditional branch */
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MIPS_DEBUG("unconditional branch");
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@ -15533,7 +15560,8 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
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if (ctx->hflags & MIPS_HFLAG_BMASK) {
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#ifdef MIPS_DEBUG_DISAS
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LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc);
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LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
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"\n", ctx->pc);
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#endif
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generate_exception(ctx, EXCP_RI);
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goto out;
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@ -15626,56 +15654,56 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
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gen_branch(ctx, 4);
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} else {
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/* Conditional compact branch */
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int l1 = gen_new_label();
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int fs = gen_new_label();
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save_cpu_state(ctx, 0);
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switch (opc) {
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case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
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if (rs == 0 && rt != 0) {
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/* OPC_BLEZALC */
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tcg_gen_brcondi_tl(TCG_COND_LE, t1, 0, l1);
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
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} else if (rs != 0 && rt != 0 && rs == rt) {
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/* OPC_BGEZALC */
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tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
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} else {
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/* OPC_BGEUC */
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tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
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tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs);
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}
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break;
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case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
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if (rs == 0 && rt != 0) {
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/* OPC_BGTZALC */
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tcg_gen_brcondi_tl(TCG_COND_GT, t1, 0, l1);
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
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} else if (rs != 0 && rt != 0 && rs == rt) {
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/* OPC_BLTZALC */
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tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
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} else {
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/* OPC_BLTUC */
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tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1);
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tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs);
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}
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break;
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case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
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if (rs == 0 && rt != 0) {
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/* OPC_BLEZC */
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tcg_gen_brcondi_tl(TCG_COND_LE, t1, 0, l1);
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
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} else if (rs != 0 && rt != 0 && rs == rt) {
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/* OPC_BGEZC */
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tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
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} else {
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/* OPC_BGEC */
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tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
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tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs);
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}
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break;
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case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
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if (rs == 0 && rt != 0) {
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/* OPC_BGTZC */
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tcg_gen_brcondi_tl(TCG_COND_GT, t1, 0, l1);
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
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} else if (rs != 0 && rt != 0 && rs == rt) {
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/* OPC_BLTZC */
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tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
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} else {
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/* OPC_BLTC */
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tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1);
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tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs);
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}
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break;
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case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
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@ -15704,10 +15732,10 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
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tcg_gen_or_tl(t4, t4, input_overflow);
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if (opc == OPC_BOVC) {
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/* OPC_BOVC */
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tcg_gen_brcondi_tl(TCG_COND_NE, t4, 0, l1);
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t4, 0, fs);
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} else {
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/* OPC_BNVC */
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tcg_gen_brcondi_tl(TCG_COND_EQ, t4, 0, l1);
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0, fs);
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}
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tcg_temp_free(input_overflow);
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tcg_temp_free(t4);
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@ -15717,27 +15745,27 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
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/* OPC_BEQZALC, OPC_BNEZALC */
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if (opc == OPC_BEQZALC) {
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/* OPC_BEQZALC */
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tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t1, 0, fs);
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} else {
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/* OPC_BNEZALC */
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tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t1, 0, fs);
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}
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} else {
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/* OPC_BEQC, OPC_BNEC */
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if (opc == OPC_BEQC) {
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/* OPC_BEQC */
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tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1);
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tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs);
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} else {
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/* OPC_BNEC */
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tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1);
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tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs);
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}
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}
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break;
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case OPC_BEQZC:
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tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t0, 0, fs);
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break;
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case OPC_BNEZC:
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tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
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tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t0, 0, fs);
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break;
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default:
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MIPS_INVAL("Compact conditional branch/jump");
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@ -15746,12 +15774,11 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
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}
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/* Generating branch here as compact branches don't have delay slot */
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/* TODO: implement forbidden slot */
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gen_goto_tb(ctx, 1, ctx->pc + 4);
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gen_set_label(l1);
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gen_goto_tb(ctx, 0, ctx->btarget);
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gen_goto_tb(ctx, 1, ctx->btarget);
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gen_set_label(fs);
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ctx->hflags |= MIPS_HFLAG_FBNSLOT;
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MIPS_DEBUG("Compact conditional branch");
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ctx->bstate = BS_BRANCH;
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}
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out:
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@ -15969,6 +15996,16 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
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op1 = MASK_SPECIAL(ctx->opcode);
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switch (op1) {
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case OPC_SLL: /* Shift with immediate */
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if (sa == 5 && rd == 0 &&
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rs == 0 && rt == 0) { /* PAUSE */
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if ((ctx->insn_flags & ISA_MIPS32R6) &&
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(ctx->hflags & MIPS_HFLAG_BMASK)) {
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MIPS_DEBUG("CTI in delay / forbidden slot");
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generate_exception(ctx, EXCP_RI);
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break;
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}
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}
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/* Fallthrough */
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case OPC_SRA:
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gen_shift_imm(ctx, op1, rd, rt, sa);
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break;
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@ -17567,7 +17604,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
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int num_insns;
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int max_insns;
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int insn_bytes;
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int is_delay;
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int is_slot;
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if (search_pc)
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qemu_log("search pc %d\n", search_pc);
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@ -17632,7 +17669,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
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gen_io_start();
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is_delay = ctx.hflags & MIPS_HFLAG_BMASK;
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is_slot = ctx.hflags & MIPS_HFLAG_BMASK;
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if (!(ctx.hflags & MIPS_HFLAG_M16)) {
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ctx.opcode = cpu_ldl_code(env, ctx.pc);
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insn_bytes = 4;
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@ -17650,12 +17687,14 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
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}
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if (ctx.hflags & MIPS_HFLAG_BMASK) {
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if (!(ctx.hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32))) {
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is_delay = 1;
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/* force to generate branch as no delay slot is required */
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if (!(ctx.hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
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MIPS_HFLAG_FBNSLOT))) {
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/* force to generate branch as there is neither delay nor
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forbidden slot */
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is_slot = 1;
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}
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}
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if (is_delay) {
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if (is_slot) {
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gen_branch(&ctx, insn_bytes);
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}
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ctx.pc += insn_bytes;
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