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target-arm: Convert cp15 crn=9 registers
Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme. Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This is a change from previous behaviour, but a return to the behaviour of commit c3d2689d when OMAP1 support was first added -- subsequent commits have clearly accidentally relegated the OMAPCP RAZ condition to only a subset of the crn=9 space when adding support for other cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
parent
06d76f319f
commit
34f9052967
@ -23,6 +23,7 @@
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#endif
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#include "sysemu.h"
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static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
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{
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@ -390,6 +391,14 @@ static void cortex_m3_initfn(Object *obj)
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cpu->midr = ARM_CPUID_CORTEXM3;
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}
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static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
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{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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REGINFO_SENTINEL
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};
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static void cortex_a8_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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@ -421,6 +430,7 @@ static void cortex_a8_initfn(Object *obj)
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cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
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cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
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cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
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define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
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}
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static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
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@ -498,6 +508,29 @@ static void cortex_a9_initfn(Object *obj)
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}
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}
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#ifndef CONFIG_USER_ONLY
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static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t *value)
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{
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/* Linux wants the number of processors from here.
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* Might as well set the interrupt-controller bit too.
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*/
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*value = ((smp_cpus - 1) << 24) | (1 << 23);
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return 0;
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}
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#endif
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static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
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#ifndef CONFIG_USER_ONLY
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{ .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
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.access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
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.writefn = arm_cp_write_ignore, },
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#endif
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{ .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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REGINFO_SENTINEL
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};
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static void cortex_a15_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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@ -533,6 +566,7 @@ static void cortex_a15_initfn(Object *obj)
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cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
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cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
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cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
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define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
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}
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static void ti925t_initfn(Object *obj)
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@ -183,6 +183,16 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
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*/
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{ .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
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.access = PL1_W, .type = ARM_CP_WFI },
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/* L1 cache lockdown. Not architectural in v6 and earlier but in practice
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* implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
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* OMAPCP will override this space.
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*/
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{ .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
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.resetvalue = 0 },
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{ .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
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.resetvalue = 0 },
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REGINFO_SENTINEL
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};
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@ -703,6 +713,9 @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
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{ .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
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.opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .type = ARM_CP_OVERRIDE,
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.writefn = omap_cachemaint_write },
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{ .name = "C9", .cp = 15, .crn = 9,
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.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
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.type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
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REGINFO_SENTINEL
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};
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@ -763,6 +776,15 @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
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REGINFO_SENTINEL
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};
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static const ARMCPRegInfo strongarm_cp_reginfo[] = {
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/* Ignore ReadBuffer accesses */
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{ .name = "C9_READBUFFER", .cp = 15, .crn = 9,
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.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
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.resetvalue = 0 },
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REGINFO_SENTINEL
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};
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void register_cp_regs_for_features(ARMCPU *cpu)
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{
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/* Register all the coprocessor registers based on feature bits */
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@ -828,6 +850,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
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define_arm_cp_regs(cpu, omap_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
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define_arm_cp_regs(cpu, strongarm_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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define_arm_cp_regs(cpu, xscale_cp_reginfo);
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}
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@ -1962,40 +1987,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
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break;
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case 4: /* Reserved. */
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goto bad_reg;
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case 9:
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if (arm_feature(env, ARM_FEATURE_OMAPCP))
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break;
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if (arm_feature(env, ARM_FEATURE_STRONGARM))
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break; /* Ignore ReadBuffer access */
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switch (crm) {
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case 0: /* Cache lockdown. */
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switch (op1) {
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case 0: /* L1 cache. */
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switch (op2) {
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case 0:
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env->cp15.c9_data = val;
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break;
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case 1:
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env->cp15.c9_insn = val;
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break;
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default:
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goto bad_reg;
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}
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break;
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case 1: /* L2 cache. */
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/* Ignore writes to L2 lockdown/auxiliary registers. */
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break;
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default:
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goto bad_reg;
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}
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break;
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case 1: /* TCM memory region registers. */
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/* Not implemented. */
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goto bad_reg;
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default:
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goto bad_reg;
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}
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break;
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case 12: /* Reserved. */
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goto bad_reg;
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}
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@ -2135,51 +2126,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
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}
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case 4: /* Reserved. */
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goto bad_reg;
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case 9:
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switch (crm) {
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case 0: /* Cache lockdown */
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switch (op1) {
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case 0: /* L1 cache. */
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if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
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return 0;
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}
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switch (op2) {
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case 0:
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return env->cp15.c9_data;
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case 1:
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return env->cp15.c9_insn;
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default:
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goto bad_reg;
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}
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case 1: /* L2 cache */
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/* L2 Lockdown and Auxiliary control. */
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switch (op2) {
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case 0:
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/* L2 cache lockdown (A8 only) */
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return 0;
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case 2:
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/* L2 cache auxiliary control (A8) or control (A15) */
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if (ARM_CPUID(env) == ARM_CPUID_CORTEXA15) {
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/* Linux wants the number of processors from here.
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* Might as well set the interrupt-controller bit too.
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*/
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return ((smp_cpus - 1) << 24) | (1 << 23);
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}
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return 0;
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case 3:
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/* L2 cache extended control (A15) */
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return 0;
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default:
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goto bad_reg;
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}
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default:
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goto bad_reg;
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}
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break;
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default:
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goto bad_reg;
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}
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break;
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case 11: /* TCM DMA control. */
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case 12: /* Reserved. */
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goto bad_reg;
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