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m68k: Replace gen_im32() by tcg_const_i32()
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
This commit is contained in:
Laurent Vivier
Stefan Hajnoczi
parent
a9899996c8
commit
351326a618
@ -171,9 +171,6 @@ typedef void (*disas_proc)(DisasContext *, uint16_t);
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static void disas_##name (DisasContext *s, uint16_t insn)
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#endif
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/* FIXME: Remove this. */
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#define gen_im32(val) tcg_const_i32(val)
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/* Generate a load from the specified address. Narrow values are
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sign extended to full register width. */
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static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
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@ -339,7 +336,7 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
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if ((ext & 0x80) == 0) {
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/* base not suppressed */
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if (IS_NULL_QREG(base)) {
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base = gen_im32(offset + bd);
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base = tcg_const_i32(offset + bd);
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bd = 0;
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}
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if (!IS_NULL_QREG(add)) {
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@ -355,7 +352,7 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
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add = tmp;
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}
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} else {
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add = gen_im32(bd);
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add = tcg_const_i32(bd);
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}
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if ((ext & 3) != 0) {
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/* memory indirect */
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@ -536,15 +533,15 @@ static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
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case 0: /* Absolute short. */
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offset = ldsw_code(s->pc);
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s->pc += 2;
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return gen_im32(offset);
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return tcg_const_i32(offset);
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case 1: /* Absolute long. */
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offset = read_im32(s);
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return gen_im32(offset);
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return tcg_const_i32(offset);
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case 2: /* pc displacement */
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offset = s->pc;
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offset += ldsw_code(s->pc);
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s->pc += 2;
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return gen_im32(offset);
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return tcg_const_i32(offset);
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case 3: /* pc index+displacement. */
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return gen_lea_indexed(s, opsize, NULL_QREG);
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case 4: /* Immediate. */
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@ -1209,16 +1206,16 @@ DISAS_INSN(arith_im)
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break;
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case 2: /* subi */
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tcg_gen_mov_i32(dest, src1);
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gen_helper_xflag_lt(QREG_CC_X, dest, gen_im32(im));
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gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
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tcg_gen_subi_i32(dest, dest, im);
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gen_update_cc_add(dest, gen_im32(im));
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gen_update_cc_add(dest, tcg_const_i32(im));
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s->cc_op = CC_OP_SUB;
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break;
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case 3: /* addi */
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tcg_gen_mov_i32(dest, src1);
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tcg_gen_addi_i32(dest, dest, im);
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gen_update_cc_add(dest, gen_im32(im));
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gen_helper_xflag_lt(QREG_CC_X, dest, gen_im32(im));
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gen_update_cc_add(dest, tcg_const_i32(im));
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gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
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s->cc_op = CC_OP_ADD;
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break;
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case 5: /* eori */
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@ -1228,7 +1225,7 @@ DISAS_INSN(arith_im)
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case 6: /* cmpi */
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tcg_gen_mov_i32(dest, src1);
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tcg_gen_subi_i32(dest, dest, im);
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gen_update_cc_add(dest, gen_im32(im));
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gen_update_cc_add(dest, tcg_const_i32(im));
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s->cc_op = CC_OP_SUB;
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break;
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default:
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@ -1324,8 +1321,8 @@ DISAS_INSN(clr)
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default:
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abort();
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}
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DEST_EA(insn, opsize, gen_im32(0), NULL);
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gen_logic_cc(s, gen_im32(0));
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DEST_EA(insn, opsize, tcg_const_i32(0), NULL);
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gen_logic_cc(s, tcg_const_i32(0));
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}
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static TCGv gen_get_ccr(DisasContext *s)
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@ -1589,7 +1586,7 @@ DISAS_INSN(jump)
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}
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if ((insn & 0x40) == 0) {
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/* jsr */
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gen_push(s, gen_im32(s->pc));
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gen_push(s, tcg_const_i32(s->pc));
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}
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gen_jmp(s, tmp);
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}
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@ -1617,7 +1614,7 @@ DISAS_INSN(addsubq)
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tcg_gen_addi_i32(dest, dest, val);
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}
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} else {
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src2 = gen_im32(val);
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src2 = tcg_const_i32(val);
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if (insn & 0x0100) {
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gen_helper_xflag_lt(QREG_CC_X, dest, src2);
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tcg_gen_subi_i32(dest, dest, val);
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@ -1666,7 +1663,7 @@ DISAS_INSN(branch)
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}
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if (op == 1) {
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/* bsr */
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gen_push(s, gen_im32(s->pc));
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gen_push(s, tcg_const_i32(s->pc));
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}
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gen_flush_cc_op(s);
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if (op > 1) {
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@ -1757,7 +1754,7 @@ DISAS_INSN(mov3q)
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val = (insn >> 9) & 7;
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if (val == 0)
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val = -1;
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src = gen_im32(val);
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src = tcg_const_i32(val);
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gen_logic_cc(s, src);
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DEST_EA(insn, OS_LONG, src, NULL);
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}
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@ -1883,7 +1880,7 @@ DISAS_INSN(shift_im)
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tmp = (insn >> 9) & 7;
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if (tmp == 0)
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tmp = 8;
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shift = gen_im32(tmp);
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shift = tcg_const_i32(tmp);
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/* No need to flush flags becuse we know we will set C flag. */
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if (insn & 0x100) {
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gen_helper_shl_cc(reg, cpu_env, reg, shift);
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@ -2191,7 +2188,7 @@ DISAS_INSN(fpu)
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switch ((ext >> 10) & 7) {
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case 4: /* FPCR */
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/* Not implemented. Always return zero. */
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tmp32 = gen_im32(0);
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tmp32 = tcg_const_i32(0);
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break;
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case 1: /* FPIAR */
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case 2: /* FPSR */
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@ -2592,7 +2589,7 @@ DISAS_INSN(mac)
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/* Skip the accumulate if the value is already saturated. */
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l1 = gen_new_label();
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tmp = tcg_temp_new();
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gen_op_and32(tmp, QREG_MACSR, gen_im32(MACSR_PAV0 << acc));
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gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
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gen_op_jmp_nz32(tmp, l1);
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}
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#endif
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@ -2626,7 +2623,7 @@ DISAS_INSN(mac)
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/* Skip the accumulate if the value is already saturated. */
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l1 = gen_new_label();
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tmp = tcg_temp_new();
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gen_op_and32(tmp, QREG_MACSR, gen_im32(MACSR_PAV0 << acc));
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gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
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gen_op_jmp_nz32(tmp, l1);
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}
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#endif
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